Merge pull request #1404 from soby-mathew/sm/bl_layout_change
ARM platforms: Change memory layout and update documentation
This commit is contained in:
commit
4b55732583
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@ -516,8 +516,8 @@ This functionality can be tested with FVP loading the image directly
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in memory and changing the address where the system jumps at reset.
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For example:
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-C cluster0.cpu0.RVBAR=0x4014000
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--data cluster0.cpu0=bl2.bin@0x4014000
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-C cluster0.cpu0.RVBAR=0x4020000
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--data cluster0.cpu0=bl2.bin@0x4020000
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With this configuration, FVP is like a platform of the first case,
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where the Boot ROM jumps always to the same address. For simplification,
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@ -1743,17 +1743,20 @@ The following list describes the memory layout on the Arm development platforms:
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this is also used for the MHU payload when passing messages to and from the
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SCP.
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- Another 4 KB page is reserved for passing memory layout between BL1 and BL2
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and also the dynamic firmware configurations.
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- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On
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Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write
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data are relocated to the top of Trusted SRAM at runtime.
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- BL2 is loaded below BL1 RW
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- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP\_MIN),
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is loaded at the top of the Trusted SRAM, such that its NOBITS sections will
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overwrite BL1 R/W data. This implies that BL1 global variables remain valid
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only until execution reaches the EL3 Runtime Software entry point during a
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cold boot.
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- BL2 is loaded below EL3 Runtime Software.
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overwrite BL1 R/W data and BL2. This implies that BL1 global variables
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remain valid only until execution reaches the EL3 Runtime Software entry
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point during a cold boot.
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- On Juno, SCP\_BL2 is loaded temporarily into the EL3 Runtime Software memory
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region and transfered to the SCP before being overwritten by EL3 Runtime
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@ -1766,9 +1769,8 @@ The following list describes the memory layout on the Arm development platforms:
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- Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
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controller)
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When BL32 (for AArch64) is loaded into Trusted SRAM, its NOBITS sections
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are allowed to overlay BL2. This memory layout is designed to give the
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BL32 image as much memory as possible when it is loaded into Trusted SRAM.
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When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below
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BL31.
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When LOAD\_IMAGE\_V2 is disabled the memory regions for the overlap detection
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mechanism at boot time are defined as follows (shown per API):
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@ -1814,21 +1816,32 @@ an example.
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Note: Loading the BL32 image in TZC secured DRAM doesn't change the memory
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layout of the other images in Trusted SRAM.
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**FVP with TSP in Trusted SRAM (default option):**
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**FVP with TSP in Trusted SRAM with firmware configs :**
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(These diagrams only cover the AArch64 case)
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::
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DRAM
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0xffffffff +----------+
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: :
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|----------|
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|HW_CONFIG |
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0x83000000 |----------| (non-secure)
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| |
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0x80000000 +----------+
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Trusted SRAM
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0x04040000 +----------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS |
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0x04040000 +----------+ loaded by BL2 +----------------+
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| BL1 (rw) | <<<<<<<<<<<<< | |
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|----------| <<<<<<<<<<<<< | BL31 NOBITS |
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| BL2 | <<<<<<<<<<<<< | |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL31 PROGBITS |
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|----------| ------------------
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| BL2 | <<<<<<<<<<<<< | BL32 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL32 PROGBITS |
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0x04001000 +----------+ ------------------
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| | <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL32 |
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0x04002000 +----------+ +----------------+
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|fw_configs|
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0x04001000 +----------+
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| Shared |
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0x04000000 +----------+
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@ -1837,7 +1850,7 @@ layout of the other images in Trusted SRAM.
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| BL1 (ro) |
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0x00000000 +----------+
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**FVP with TSP in Trusted DRAM with TB_FW_CONFIG and HW_CONFIG :**
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**FVP with TSP in Trusted DRAM with firmware configs (default option):**
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::
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@ -1856,17 +1869,15 @@ layout of the other images in Trusted SRAM.
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0x06000000 +--------------+
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Trusted SRAM
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0x04040000 +--------------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS |
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0x04040000 +--------------+ loaded by BL2 +----------------+
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| BL1 (rw) | <<<<<<<<<<<<< | |
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|--------------| <<<<<<<<<<<<< | BL31 NOBITS |
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| BL2 | <<<<<<<<<<<<< | |
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|--------------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL31 PROGBITS |
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|--------------| ------------------
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| BL2 |
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|--------------|
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| |
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|--------------|
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| TB_FW_CONFIG |
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|--------------|
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| | +----------------+
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+--------------+
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| fw_configs |
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0x04001000 +--------------+
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| Shared |
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0x04000000 +--------------+
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@ -1876,7 +1887,7 @@ layout of the other images in Trusted SRAM.
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| BL1 (ro) |
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0x00000000 +--------------+
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**FVP with TSP in TZC-Secured DRAM:**
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**FVP with TSP in TZC-Secured DRAM with firmware configs :**
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::
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@ -1885,19 +1896,22 @@ layout of the other images in Trusted SRAM.
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| BL32 | (secure)
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0xff000000 +----------+
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| |
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: : (non-secure)
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|----------|
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|HW_CONFIG |
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0x83000000 |----------| (non-secure)
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| |
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0x80000000 +----------+
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Trusted SRAM
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0x04040000 +----------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS |
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0x04040000 +----------+ loaded by BL2 +----------------+
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| BL1 (rw) | <<<<<<<<<<<<< | |
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|----------| <<<<<<<<<<<<< | BL31 NOBITS |
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| BL2 | <<<<<<<<<<<<< | |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL31 PROGBITS |
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|----------| ------------------
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| BL2 |
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|----------|
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| |
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| | +----------------+
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0x04002000 +----------+
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|fw_configs|
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0x04001000 +----------+
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| Shared |
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0x04000000 +----------+
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@ -1907,7 +1921,7 @@ layout of the other images in Trusted SRAM.
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| BL1 (ro) |
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0x00000000 +----------+
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**Juno with BL32 in Trusted SRAM (default option):**
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**Juno with BL32 in Trusted SRAM :**
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::
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@ -1921,19 +1935,21 @@ layout of the other images in Trusted SRAM.
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0x08000000 +----------+ BL31 is loaded
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after SCP_BL2 has
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Trusted SRAM been sent to SCP
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0x04040000 +----------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS |
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0x04040000 +----------+ loaded by BL2 +----------------+
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| BL1 (rw) | <<<<<<<<<<<<< | |
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|----------| <<<<<<<<<<<<< | BL31 NOBITS |
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| BL2 | <<<<<<<<<<<<< | |
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|----------| <<<<<<<<<<<<< |----------------|
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| SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
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|----------| ------------------
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| BL2 | <<<<<<<<<<<<< | BL32 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL32 PROGBITS |
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0x04001000 +----------+ ------------------
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| | <<<<<<<<<<<<< | BL32 |
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| | +----------------+
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| |
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0x04001000 +----------+
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| MHU |
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0x04000000 +----------+
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**Juno with BL32 in TZC-secured DRAM:**
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**Juno with BL32 in TZC-secured DRAM :**
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::
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@ -1956,14 +1972,13 @@ layout of the other images in Trusted SRAM.
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0x08000000 +----------+ BL31 is loaded
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after SCP_BL2 has
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Trusted SRAM been sent to SCP
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0x04040000 +----------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS |
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0x04040000 +----------+ loaded by BL2 +----------------+
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| BL1 (rw) | <<<<<<<<<<<<< | |
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|----------| <<<<<<<<<<<<< | BL31 NOBITS |
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| BL2 | <<<<<<<<<<<<< | |
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|----------| <<<<<<<<<<<<< |----------------|
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| SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
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|----------| ------------------
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| BL2 |
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|----------|
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| |
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|----------| +----------------+
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0x04001000 +----------+
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| MHU |
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0x04000000 +----------+
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@ -1928,7 +1928,7 @@ with 8 CPUs using the AArch32 build of TF-A.
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-C cluster1.cpu1.RVBAR=0x04001000 \
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-C cluster1.cpu2.RVBAR=0x04001000 \
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-C cluster1.cpu3.RVBAR=0x04001000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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@ -1959,7 +1959,7 @@ boot Linux with 8 CPUs using the AArch64 build of TF-A.
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-C cluster1.cpu2.RVBARADDR=0x04020000 \
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-C cluster1.cpu3.RVBARADDR=0x04020000 \
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--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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@ -1982,7 +1982,7 @@ boot Linux with 4 CPUs using the AArch32 build of TF-A.
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-C cluster0.cpu1.RVBARADDR=0x04001000 \
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-C cluster0.cpu2.RVBARADDR=0x04001000 \
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-C cluster0.cpu3.RVBARADDR=0x04001000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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@ -93,21 +93,19 @@
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#endif
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/*
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* PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
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* little space for growth.
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* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
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* calculated using the current BL31 PROGBITS debug size plus the sizes of
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* BL2 and BL1-RW
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*/
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#if ENABLE_SPM
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# define PLAT_ARM_MAX_BL31_SIZE 0x40000
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#else
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# define PLAT_ARM_MAX_BL31_SIZE 0x20000
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#endif
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#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
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#ifdef AARCH32
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/*
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* PLAT_ARM_MAX_BL32_SIZE is calculated for SP_MIN as the AArch32 Secure
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* Payload.
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* Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
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* calculated using the current SP_MIN PROGBITS debug size plus the sizes of
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* BL2 and BL1-RW
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*/
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# define PLAT_ARM_MAX_BL32_SIZE 0x1D000
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# define PLAT_ARM_MAX_BL32_SIZE 0x3B000
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#endif
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#endif /* ARM_BOARD_OPTIMISE_MEM */
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@ -317,7 +317,7 @@
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* and limit. Leave enough space of BL2 meminfo.
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*/
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#define ARM_TB_FW_CONFIG_BASE ARM_BL_RAM_BASE + sizeof(meminfo_t)
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#define ARM_TB_FW_CONFIG_LIMIT BL2_BASE
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#define ARM_TB_FW_CONFIG_LIMIT ARM_BL_RAM_BASE + PAGE_SIZE
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/*******************************************************************************
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* BL1 specific defines.
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@ -338,32 +338,18 @@
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/*******************************************************************************
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* BL2 specific defines.
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******************************************************************************/
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#if ARM_BL31_IN_DRAM
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#if BL2_AT_EL3
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/* Put BL2 in the middle of the Trusted SRAM */
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#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
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(PLAT_ARM_TRUSTED_SRAM_SIZE >> 1))
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#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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#else
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/*
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* For AArch64 BL31 is loaded in the DRAM.
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* Put BL2 just below BL1.
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*/
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#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_LIMIT BL1_RW_BASE
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#elif BL2_AT_EL3
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#define BL2_BASE ARM_BL_RAM_BASE
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#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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#elif defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME
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/*
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* Put BL2 just below BL32.
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*/
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#define BL2_BASE (BL32_BASE - PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_LIMIT BL32_BASE
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#else
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/*
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* Put BL2 just below BL31.
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*/
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#define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_LIMIT BL31_BASE
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#endif
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/*******************************************************************************
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@ -384,13 +370,10 @@
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(PLAT_ARM_TRUSTED_SRAM_SIZE >> 1))
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#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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#else
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/*
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* Put BL31 at the top of the Trusted SRAM.
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*/
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#define BL31_BASE (ARM_BL_RAM_BASE + \
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ARM_BL_RAM_SIZE - \
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PLAT_ARM_MAX_BL31_SIZE)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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/* Put BL31 below BL2 in the Trusted SRAM.*/
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#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
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- PLAT_ARM_MAX_BL31_SIZE)
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#define BL31_PROGBITS_LIMIT BL2_BASE
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#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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#endif
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|
@ -399,15 +382,17 @@
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* BL32 specific defines for EL3 runtime in AArch32 mode
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******************************************************************************/
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# if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
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/* SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM to BL32 */
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# define BL32_BASE ARM_BL_RAM_BASE
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/*
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* SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding
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* the page reserved for fw_configs) to BL32
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*/
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# define BL32_BASE ARM_TB_FW_CONFIG_LIMIT
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# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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# else
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/* Put BL32 at the top of the Trusted SRAM.*/
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# define BL32_BASE (ARM_BL_RAM_BASE + \
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ARM_BL_RAM_SIZE - \
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PLAT_ARM_MAX_BL32_SIZE)
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# define BL32_PROGBITS_LIMIT BL1_RW_BASE
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/* Put BL32 below BL2 in the Trusted SRAM.*/
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# define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
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- PLAT_ARM_MAX_BL32_SIZE)
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# define BL32_PROGBITS_LIMIT BL2_BASE
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# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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# endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */
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|
@ -438,8 +423,8 @@
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# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
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# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
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# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
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# define TSP_PROGBITS_LIMIT BL2_BASE
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# define BL32_BASE ARM_BL_RAM_BASE
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# define TSP_PROGBITS_LIMIT BL31_BASE
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# define BL32_BASE ARM_TB_FW_CONFIG_LIMIT
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# define BL32_LIMIT BL31_BASE
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# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
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# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
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|
|
|
@ -158,14 +158,14 @@
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/*
|
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* Load address of SCP_BL2 in CSS platform ports
|
||||
* SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1
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* rw data. Once SCP_BL2 is transferred to the SCP, it is discarded and BL31
|
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* is loaded over the top.
|
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* rw data or BL2. Once SCP_BL2 is transferred to the SCP, it is discarded and
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* BL31 is loaded over the top.
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*/
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#define SCP_BL2_BASE (BL1_RW_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE)
|
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#define SCP_BL2_LIMIT BL1_RW_BASE
|
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#define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE)
|
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#define SCP_BL2_LIMIT BL2_BASE
|
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#define SCP_BL2U_BASE (BL1_RW_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE)
|
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#define SCP_BL2U_LIMIT BL1_RW_BASE
|
||||
#define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE)
|
||||
#define SCP_BL2U_LIMIT BL2_BASE
|
||||
#endif /* CSS_LOAD_SCP_IMAGES */
|
||||
|
||||
/* Load address of Non-Secure Image for CSS platform ports */
|
||||
|
|
|
@ -225,12 +225,6 @@ ifneq (${BL2_AT_EL3}, 0)
|
|||
override BL1_SOURCES =
|
||||
endif
|
||||
|
||||
ifeq (${ENABLE_SPM},1)
|
||||
ifneq (${ARM_BL31_IN_DRAM},1)
|
||||
$(error "Error: SPM needs BL31 to be located in DRAM.")
|
||||
endif
|
||||
endif
|
||||
|
||||
include plat/arm/board/common/board_common.mk
|
||||
include plat/arm/common/arm_common.mk
|
||||
|
||||
|
|
|
@ -139,22 +139,21 @@
|
|||
#endif
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
|
||||
* little space for growth.
|
||||
* SCP_BL2 image is loaded into the space BL31 -> BL1_RW_BASE.
|
||||
* For TBB use case, PLAT_ARM_MAX_BL1_RW_SIZE has been increased and therefore
|
||||
* PLAT_ARM_MAX_BL31_SIZE has been increased to ensure SCP_BL2 has the same
|
||||
* space available.
|
||||
* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
|
||||
* calculated using the current BL31 PROGBITS debug size plus the sizes of
|
||||
* BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE.
|
||||
* Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE.
|
||||
*/
|
||||
#define PLAT_ARM_MAX_BL31_SIZE 0x1E000
|
||||
#define PLAT_ARM_MAX_BL31_SIZE 0x3E000
|
||||
|
||||
#if JUNO_AARCH32_EL3_RUNTIME
|
||||
/*
|
||||
* PLAT_ARM_MAX_BL32_SIZE is calculated for SP_MIN as the AArch32 Secure
|
||||
* Payload. We also need to take care of SCP_BL2 size as well, as the SCP_BL2
|
||||
* is loaded into the space BL32 -> BL1_RW_BASE
|
||||
* Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
|
||||
* calculated using the current BL32 PROGBITS debug size plus the sizes of
|
||||
* BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE.
|
||||
* Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE.
|
||||
*/
|
||||
# define PLAT_ARM_MAX_BL32_SIZE 0x1E000
|
||||
#define PLAT_ARM_MAX_BL32_SIZE 0x3E000
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
@ -25,18 +25,10 @@
|
|||
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
|
||||
|
||||
/*
|
||||
* Check that BL2_BASE is atleast a page over ARM_BL_RAM_BASE. The page is for
|
||||
* `meminfo_t` data structure and TB_FW_CONFIG passed from BL1. Not needed
|
||||
* when BL2 is compiled for BL_AT_EL3 as BL2 doesn't need any info from BL1 and
|
||||
* BL2 is loaded at base of usable SRAM.
|
||||
* Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is
|
||||
* for `meminfo_t` data structure and fw_configs passed from BL1.
|
||||
*/
|
||||
#if BL2_AT_EL3
|
||||
#define BL1_MEMINFO_OFFSET 0x0
|
||||
#else
|
||||
#define BL1_MEMINFO_OFFSET PAGE_SIZE
|
||||
#endif
|
||||
|
||||
CASSERT(BL2_BASE >= (ARM_BL_RAM_BASE + BL1_MEMINFO_OFFSET), assert_bl2_base_overflows);
|
||||
CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
|
||||
|
||||
/* Weak definitions may be overridden in specific ARM standard platform */
|
||||
#pragma weak bl2_early_platform_setup2
|
||||
|
|
|
@ -25,6 +25,11 @@
|
|||
static entry_point_info_t bl32_image_ep_info;
|
||||
static entry_point_info_t bl33_image_ep_info;
|
||||
|
||||
/*
|
||||
* Check that BL31_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page
|
||||
* is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
|
||||
*/
|
||||
CASSERT(BL31_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl31_base_overflows);
|
||||
|
||||
/* Weak definitions may be overridden in specific ARM standard platform */
|
||||
#pragma weak bl31_early_platform_setup2
|
||||
|
|
|
@ -143,8 +143,8 @@ void arm_bl2_dyn_cfg_init(void)
|
|||
if (check_uptr_overflow(image_base, image_size) != 0)
|
||||
continue;
|
||||
|
||||
/* Ensure the configs don't overlap with BL2 */
|
||||
if ((image_base > BL2_BASE) || ((image_base + image_size) > BL2_BASE))
|
||||
/* Ensure the configs don't overlap with BL31 */
|
||||
if ((image_base > BL31_BASE) || ((image_base + image_size) > BL31_BASE))
|
||||
continue;
|
||||
|
||||
/* Ensure the configs are loaded in a valid address */
|
||||
|
|
|
@ -22,6 +22,11 @@ static entry_point_info_t bl33_image_ep_info;
|
|||
#pragma weak sp_min_plat_arch_setup
|
||||
#pragma weak plat_arm_sp_min_early_platform_setup
|
||||
|
||||
/*
|
||||
* Check that BL32_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page
|
||||
* is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
|
||||
*/
|
||||
CASSERT(BL32_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl32_base_overflows);
|
||||
|
||||
/*******************************************************************************
|
||||
* Return a pointer to the 'entry_point_info' structure of the next image for the
|
||||
|
|
|
@ -47,16 +47,16 @@ typedef struct {
|
|||
} cmd_data_payload_t;
|
||||
|
||||
/*
|
||||
* All CSS platforms load SCP_BL2/SCP_BL2U just below BL rw-data and above
|
||||
* BL2/BL2U (this is where BL31 usually resides except when ARM_BL31_IN_DRAM is
|
||||
* set. Ensure that SCP_BL2/SCP_BL2U do not overflow into BL1 rw-data nor
|
||||
* BL2/BL2U.
|
||||
* All CSS platforms load SCP_BL2/SCP_BL2U just below BL2 (this is where BL31
|
||||
* usually resides except when ARM_BL31_IN_DRAM is
|
||||
* set). Ensure that SCP_BL2/SCP_BL2U do not overflow into shared RAM and
|
||||
* the tb_fw_config.
|
||||
*/
|
||||
CASSERT(SCP_BL2_LIMIT <= BL1_RW_BASE, assert_scp_bl2_overwrite_bl1);
|
||||
CASSERT(SCP_BL2U_LIMIT <= BL1_RW_BASE, assert_scp_bl2u_overwrite_bl1);
|
||||
CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
|
||||
CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
|
||||
|
||||
CASSERT(SCP_BL2_BASE >= BL2_LIMIT, assert_scp_bl2_overwrite_bl2);
|
||||
CASSERT(SCP_BL2U_BASE >= BL2U_LIMIT, assert_scp_bl2u_overwrite_bl2u);
|
||||
CASSERT(SCP_BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
|
||||
CASSERT(SCP_BL2U_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
|
||||
|
||||
static void scp_boot_message_start(void)
|
||||
{
|
||||
|
|
|
@ -34,17 +34,17 @@ int css_scp_boot_image_xfer(void *image, unsigned int image_size);
|
|||
int css_scp_boot_ready(void);
|
||||
|
||||
#if CSS_LOAD_SCP_IMAGES
|
||||
/*
|
||||
* All CSS platforms load SCP_BL2/SCP_BL2U just below BL rw-data and above
|
||||
* BL2/BL2U (this is where BL31 usually resides except when ARM_BL31_IN_DRAM is
|
||||
* set. Ensure that SCP_BL2/SCP_BL2U do not overflow into BL1 rw-data nor
|
||||
* BL2/BL2U.
|
||||
*/
|
||||
CASSERT(SCP_BL2_LIMIT <= BL1_RW_BASE, assert_scp_bl2_limit_overwrite_bl1);
|
||||
CASSERT(SCP_BL2U_LIMIT <= BL1_RW_BASE, assert_scp_bl2u_limit_overwrite_bl1);
|
||||
|
||||
CASSERT(SCP_BL2_BASE >= BL2_LIMIT, assert_scp_bl2_overwrite_bl2);
|
||||
CASSERT(SCP_BL2U_BASE >= BL2U_LIMIT, assert_scp_bl2u_overwrite_bl2u);
|
||||
/*
|
||||
* All CSS platforms load SCP_BL2/SCP_BL2U just below BL2 (this is where BL31
|
||||
* usually resides except when ARM_BL31_IN_DRAM is
|
||||
* set). Ensure that SCP_BL2/SCP_BL2U do not overflow into tb_fw_config.
|
||||
*/
|
||||
CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
|
||||
CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
|
||||
|
||||
CASSERT(SCP_BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
|
||||
CASSERT(SCP_BL2U_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
|
||||
#endif
|
||||
|
||||
#endif /* __CSS_SCP_H__ */
|
||||
|
|
Loading…
Reference in New Issue