Tegra194: memctrl: remove support to reconfigure MSS
As bpmp-fw is running at the same time as ATF, and the mss client reconfiguration sequence involves performing a hot flush resets on bpmp, there is a chance that bpmp-fw is trying to perform accesses while the hot flush is active. Therefore, the mss client reconfigure has been moved to System Suspend resume fw and bootloader, and it can be removed from here. Change-Id: I34019ad12abea9681f5e180af6bc86f2c4c6fc74 Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
This commit is contained in:
Stefan Kristiansson
Varun Wadekar
parent
f617868678
commit
4b74f6d24c
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@ -271,413 +271,6 @@ const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
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mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, DISABLE)
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};
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/* To be called by common memctrl_v2.c */
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static void tegra194_memctrl_reconfig_mss_clients(void)
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{
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uint32_t reg_val, wdata_0, wdata_1, wdata_2;
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wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB;
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if (tegra_platform_is_silicon()) {
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wdata_0 |= MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB;
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}
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tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
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/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
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do {
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reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
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} while ((reg_val & wdata_0) != wdata_0);
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wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB|
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MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB;
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if (tegra_platform_is_silicon()) {
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wdata_1 |= MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB;
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}
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tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
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/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
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do {
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reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
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} while ((reg_val & wdata_1) != wdata_1);
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wdata_2 = MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB;
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if (tegra_platform_is_silicon()) {
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wdata_2 |= MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB;
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}
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tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
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/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
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do {
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reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS2);
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} while ((reg_val & wdata_2) != wdata_2);
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/*
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* Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and
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* strongly ordered MSS clients.
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*
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* MC clients with default SO_DEV override still enabled at TSA:
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* EQOSW, SATAW, XUSB_DEVW, XUSB_HOSTW, PCIe0w, PCIe1w, PCIe2w,
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* PCIe3w, PCIe4w and PCIe5w.
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*/
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mc_set_tsa_w_passthrough(AONDMAW);
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mc_set_tsa_w_passthrough(AONW);
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mc_set_tsa_w_passthrough(APEDMAW);
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mc_set_tsa_w_passthrough(APEW);
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mc_set_tsa_w_passthrough(AXISW);
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mc_set_tsa_w_passthrough(BPMPDMAW);
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mc_set_tsa_w_passthrough(BPMPW);
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mc_set_tsa_w_passthrough(EQOSW);
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mc_set_tsa_w_passthrough(ETRW);
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mc_set_tsa_w_passthrough(RCEDMAW);
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mc_set_tsa_w_passthrough(RCEW);
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mc_set_tsa_w_passthrough(SCEDMAW);
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mc_set_tsa_w_passthrough(SCEW);
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mc_set_tsa_w_passthrough(SDMMCW);
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mc_set_tsa_w_passthrough(SDMMCWA);
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mc_set_tsa_w_passthrough(SDMMCWAB);
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mc_set_tsa_w_passthrough(SESWR);
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mc_set_tsa_w_passthrough(TSECSWR);
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mc_set_tsa_w_passthrough(TSECSWRB);
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mc_set_tsa_w_passthrough(UFSHCW);
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mc_set_tsa_w_passthrough(VICSWR);
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mc_set_tsa_w_passthrough(VIFALW);
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/*
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* set HUB2 as SO_DEV_HUBID
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*/
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reg_val = tsa_read_32(PCIE0W);
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mc_set_tsa_hub2(reg_val, PCIE0W);
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reg_val = tsa_read_32(PCIE1W);
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mc_set_tsa_hub2(reg_val, PCIE1W);
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reg_val = tsa_read_32(PCIE2AW);
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mc_set_tsa_hub2(reg_val, PCIE2AW);
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reg_val = tsa_read_32(PCIE3W);
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mc_set_tsa_hub2(reg_val, PCIE3W);
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reg_val = tsa_read_32(PCIE4W);
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mc_set_tsa_hub2(reg_val, PCIE4W);
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reg_val = tsa_read_32(SATAW);
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mc_set_tsa_hub2(reg_val, SATAW);
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reg_val = tsa_read_32(XUSB_DEVW);
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mc_set_tsa_hub2(reg_val, XUSB_DEVW);
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reg_val = tsa_read_32(XUSB_HOSTW);
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mc_set_tsa_hub2(reg_val, XUSB_HOSTW);
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/*
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* Hw Bug: 200385660, 200394107
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* PCIE datapath hangs when there are more than 28 outstanding
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* requests on data backbone for x1 controller. This is seen
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* on third party PCIE IP, C1 - PCIE1W, C2 - PCIE2AW and C3 - PCIE3W.
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*
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* Setting Reorder depth limit, 16 which is < 28.
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*/
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mc_set_tsa_depth_limit(REORDER_DEPTH_LIMIT, PCIE1W);
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mc_set_tsa_depth_limit(REORDER_DEPTH_LIMIT, PCIE2AW);
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mc_set_tsa_depth_limit(REORDER_DEPTH_LIMIT, PCIE3W);
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/* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3
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* ISO clients(DISP, VI, EQOS) should never snoop caches and
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* don't need ROC/PCFIFO ordering.
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* ISO clients(EQOS) that need ordering should use PCFIFO ordering
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* and bypass ROC ordering by using FORCE_NON_COHERENT path.
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* FORCE_NON_COHERENT/FORCE_COHERENT config take precedence
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* over SMMU attributes.
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* Force all Normal memory transactions from ISO and non-ISO to be
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* non-coherent(bypass ROC, avoid cache snoop to avoid perf hit).
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* Force the SO_DEV transactions from ordered ISO clients(EQOS) to
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* non-coherent path and enable MC PCFIFO interlock for ordering.
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* Force the SO_DEV transactions from ordered non-ISO clients (PCIe,
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* XUSB, SATA) to coherent so that the transactions are
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* ordered by ROC.
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* PCFIFO ensure write ordering.
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* Read after Write ordering is maintained/enforced by MC clients.
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* Clients that need PCIe type write ordering must
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* go through ROC ordering.
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* Ordering enable for Read clients is not necessary.
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* R5's and A9 would get necessary ordering from AXI and
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* don't need ROC ordering enable:
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* - MMIO ordering is through dev mapping and MMIO
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* accesses bypass SMMU.
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* - Normal memory is accessed through SMMU and ordering is
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* ensured by client and AXI.
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* - Ack point for Normal memory is WCAM in MC.
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* - MMIO's can be early acked and AXI ensures dev memory ordering,
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* Client ensures read/write direction change ordering.
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* - See Bug 200312466 for more details.
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*/
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mc_set_txn_override(AONDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(AONDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(AONR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(AONW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(APEDMAR, CGID_TAG_ADR, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(APEDMAW, CGID_TAG_ADR, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(APER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(APEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(AXISR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(AXISW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(BPMPDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(BPMPDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(BPMPR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(BPMPW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(EQOSR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(EQOSW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(ETRR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(ETRW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(HOST1XDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(MPCORER, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
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mc_set_txn_override(MPCOREW, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
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mc_set_txn_override(NVDISPLAYR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(NVDISPLAYR1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(PCIE0R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(PCIE0R1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(PCIE0W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(PCIE1R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(PCIE1W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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if (tegra_platform_is_silicon()) {
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mc_set_txn_override(PCIE2AR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(PCIE2AW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(PCIE3R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(PCIE3W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(PCIE4R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(PCIE4W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(PCIE5R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(PCIE5W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(PCIE5R1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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}
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mc_set_txn_override(PTCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(RCEDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(RCEDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(RCER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(RCEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(SATAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(SATAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(SCEDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(SCEDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(SCER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(SCEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(SDMMCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(SDMMCRAB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(SDMMCRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(SDMMCW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(SDMMCWA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(SDMMCWAB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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/*
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* TO DO: make SESRD/WR FORCE_COHERENT once SE+TZ with SMMU is enabled.
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*/
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mc_set_txn_override(SESRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(SESWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(TSECSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(TSECSRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(TSECSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(TSECSWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(UFSHCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(UFSHCW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(VICSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(VICSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(VICSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(VIFALR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(VIFALW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(XUSB_DEVR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(XUSB_DEVW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(XUSB_HOSTR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
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mc_set_txn_override(XUSB_HOSTW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP);
|
||||
mc_set_txn_override(AXIAPR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(AXIAPW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(DLA0FALRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(DLA0FALWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(DLA0RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(DLA0RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(DLA0WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(DLA1FALRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(DLA1FALWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(DLA1RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(DLA1RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(DLA1WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(HDAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(HDAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(ISPFALR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(ISPFALW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(ISPRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(ISPRA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(ISPWA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(ISPWB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVDEC1SRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVDEC1SRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVDEC1SWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVDECSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVDECSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVDECSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVENC1SRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVENC1SRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVENC1SWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVENCSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVENCSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVENCSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVJPGSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(NVJPGSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA0RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA0RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA0RDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA0RDB1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA0RDC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA0WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA0WRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA0WRC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA1RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA1RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA1RDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA1RDB1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA1RDC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA1WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA1WRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(PVA1WRC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(VIW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
|
||||
if (tegra_platform_is_silicon()) {
|
||||
mc_set_txn_override(MIU0R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU0W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU1R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU1W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU2R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU2W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU3R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU3W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU4R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU4W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU5R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU5W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU6R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU6W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU7R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MIU7W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
}
|
||||
|
||||
/*
|
||||
* At this point, ordering can occur at SCF. So, remove PCFIFO's
|
||||
* control over ordering requests.
|
||||
*
|
||||
* Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for
|
||||
* boot and strongly ordered MSS clients
|
||||
*/
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val);
|
||||
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWA) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(3, VICSWR) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(3, APEW);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, reg_val);
|
||||
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, TSECSWRB) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, BPMPW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, AONW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
|
||||
/* EQOSW has PCFIFO order enabled. */
|
||||
reg_val |= mc_set_pcfifo_unordered_boot_so_mss(4, EQOSW);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val);
|
||||
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(5, VIFALW);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, reg_val);
|
||||
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val);
|
||||
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(7, PCIE4W) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(7, PCIE5W);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val);
|
||||
|
||||
/* Set Order Id only for the clients having non zero order id */
|
||||
reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_9_RESET_VAL, 9, XUSB_HOSTW);
|
||||
tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val);
|
||||
|
||||
reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_27_RESET_VAL, 27, PCIE0W);
|
||||
tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val);
|
||||
|
||||
reg_val = mc_client_order_id(MC_CLIENT_ORDER_ID_28_RESET_VAL, 28, PCIE4W);
|
||||
reg_val = mc_client_order_id(reg_val, 28, PCIE5W);
|
||||
tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val);
|
||||
|
||||
/*
|
||||
* Set VC Id only for the clients having different reset values like
|
||||
* SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB, TSECSWR and
|
||||
* TSECSWRB clients
|
||||
*/
|
||||
reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_0_RESET_VAL, 0, APB);
|
||||
tegra_mc_write_32(MC_HUB_PC_VC_ID_0, reg_val);
|
||||
|
||||
/* SDMMCRAB and SDMMCWAB clients */
|
||||
reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_2_RESET_VAL, 2, SD);
|
||||
tegra_mc_write_32(MC_HUB_PC_VC_ID_2, reg_val);
|
||||
|
||||
reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_4_RESET_VAL, 4, NIC);
|
||||
tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val);
|
||||
|
||||
reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_12_RESET_VAL, 12, UFSHCPC2);
|
||||
tegra_mc_write_32(MC_HUB_PC_VC_ID_12, reg_val);
|
||||
|
||||
wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
|
||||
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
|
||||
|
||||
wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
|
||||
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
|
||||
|
||||
wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL;
|
||||
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
|
||||
|
||||
reg_val = MC_COALESCE_CTRL_COALESCER_ENABLE;
|
||||
tegra_mc_write_32(MC_COALESCE_CTRL, reg_val);
|
||||
|
||||
/*
|
||||
* WAR to hardware bug 1953865: Coalescer must be disabled
|
||||
* for PVA0RDC and PVA1RDC interfaces.
|
||||
*/
|
||||
reg_val = tegra_mc_read_32(MC_COALESCE_CONFIG_6_0);
|
||||
reg_val &= ~(MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED |
|
||||
MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED);
|
||||
tegra_mc_write_32(MC_COALESCE_CONFIG_6_0, reg_val);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Struct to hold the memory controller settings
|
||||
******************************************************************************/
|
||||
|
|
@ -685,8 +278,7 @@ static tegra_mc_settings_t tegra194_mc_settings = {
|
|||
.streamid_override_cfg = tegra194_streamid_override_regs,
|
||||
.num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs),
|
||||
.streamid_security_cfg = tegra194_streamid_sec_cfgs,
|
||||
.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs),
|
||||
.reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients
|
||||
.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs)
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
Loading…
Reference in New Issue