juno: Move BL3-1 arguments from normal DRAM to trusted RAM
On Juno, BL3-1 arguments used to sit at the beginning of the normal DRAM. This patch moves them in trusted RAM. BL2 now allocates them as a platform-specific static variable. BL3-1 then copies them internally before the MMU is enabled. Change-Id: I5cf526edfab5b49925b685092ff78506a5882f49
This commit is contained in:
Sandrine Bailleux
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ae4ed84bb1
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@ -76,11 +76,9 @@ __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
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section("tzfw_coherent_mem")));
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/*******************************************************************************
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* Reference to structures which holds the arguments which need to be passed
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* to BL31
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* Structure which holds the arguments which need to be passed to BL3-1
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******************************************************************************/
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static bl31_params_t *bl2_to_bl31_params;
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static entry_point_info_t *bl31_ep_info;
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static bl2_to_bl31_params_mem_t bl31_params_mem;
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meminfo_t *bl2_plat_sec_mem_layout(void)
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{
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@ -98,46 +96,41 @@ meminfo_t *bl2_plat_sec_mem_layout(void)
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******************************************************************************/
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bl31_params_t *bl2_plat_get_bl31_params(void)
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{
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bl2_to_bl31_params_mem_t *bl31_params_mem;
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bl31_params_t *bl2_to_bl31_params;
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/*
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* Allocate the memory for all the arguments that needs to
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* be passed to BL31
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* Initialise the memory for all the arguments that needs to
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* be passed to BL3-1
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*/
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bl31_params_mem = (bl2_to_bl31_params_mem_t *)PARAMS_BASE;
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memset((void *)PARAMS_BASE, 0, sizeof(bl2_to_bl31_params_mem_t));
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memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t));
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/* Assign memory for TF related information */
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bl2_to_bl31_params = &bl31_params_mem->bl31_params;
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bl2_to_bl31_params = &bl31_params_mem.bl31_params;
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SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
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/* Fill BL31 related information */
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bl31_ep_info = &bl31_params_mem->bl31_ep_info;
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bl2_to_bl31_params->bl31_image_info = &bl31_params_mem->bl31_image_info;
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/* Fill BL3-1 related information */
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bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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/* Fill BL32 related information if it exists */
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if (BL32_BASE) {
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bl2_to_bl31_params->bl32_ep_info =
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&bl31_params_mem->bl32_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info,
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PARAM_EP, VERSION_1, 0);
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bl2_to_bl31_params->bl32_image_info =
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&bl31_params_mem->bl32_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
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PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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}
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/* Fill BL3-2 related information if it exists */
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#if BL32_BASE
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bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
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VERSION_1, 0);
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bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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#endif
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/* Fill BL33 related information */
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bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem->bl33_ep_info;
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/* Fill BL3-3 related information */
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bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
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PARAM_EP, VERSION_1, 0);
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/* UEFI expects to receive the primary CPU MPID (through x0) */
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bl2_to_bl31_params->bl33_ep_info->args.arg0 = PRIMARY_CPU;
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bl2_to_bl31_params->bl33_image_info = &bl31_params_mem->bl33_image_info;
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bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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@ -150,7 +143,7 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
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******************************************************************************/
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struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
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{
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return bl31_ep_info;
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return &bl31_params_mem.bl31_ep_info;
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}
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/*******************************************************************************
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@ -253,7 +246,7 @@ void bl2_platform_setup(void)
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/* Flush the TF params and the TF plat params */
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void bl2_plat_flush_bl31_params(void)
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{
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flush_dcache_range((unsigned long)PARAMS_BASE,
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flush_dcache_range((unsigned long)&bl31_params_mem,
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sizeof(bl2_to_bl31_params_mem_t));
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}
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@ -68,10 +68,11 @@ extern unsigned long __COHERENT_RAM_END__;
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#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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/******************************************************************************
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* Reference to structures which hold the arguments that have been passed to
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* BL31 from BL2.
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* Placeholder variables for copying the arguments that have been passed to
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* BL3-1 from BL2.
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******************************************************************************/
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static bl31_params_t *bl2_to_bl31_params;
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static entry_point_info_t bl32_ep_info;
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static entry_point_info_t bl33_ep_info;
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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@ -83,9 +84,7 @@ entry_point_info_t *bl31_get_next_image_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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next_image_info = (type == NON_SECURE) ?
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bl2_to_bl31_params->bl33_ep_info :
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bl2_to_bl31_params->bl32_ep_info;
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next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
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/* None of the images on this platform can have 0x0 as the entrypoint */
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if (next_image_info->pc)
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@ -98,10 +97,9 @@ entry_point_info_t *bl31_get_next_image_info(uint32_t type)
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* Perform any BL3-1 specific platform actions. Here is an opportunity to copy
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* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
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* are lost (potentially). This needs to be done before the MMU is initialized
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* so that the memory layout can be used while creating page tables. The 'data'
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* parameter is not used since all the information is contained in 'from_bl2'.
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* Also, BL2 has flushed this information to memory, so we are guaranteed to
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* pick up good data
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* so that the memory layout can be used while creating page tables. Also, BL2
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* has flushed this information to memory, so we are guaranteed to pick up good
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* data
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******************************************************************************/
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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@ -112,8 +110,12 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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assert(from_bl2->h.type == PARAM_BL31);
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assert(from_bl2->h.version >= VERSION_1);
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bl2_to_bl31_params = from_bl2;
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/*
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* Copy BL3-2 and BL3-3 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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bl32_ep_info = *from_bl2->bl32_ep_info;
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bl33_ep_info = *from_bl2->bl33_ep_info;
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}
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/*******************************************************************************
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@ -134,10 +134,6 @@
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#define DRAM_BASE 0x80000000
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#define DRAM_SIZE 0x80000000
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/* Base address where parameters to BL31 are stored */
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/* Juno TODO: Move BL3-1 arguments somewhere in trusted memory */
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#define PARAMS_BASE DRAM_BASE
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/* Memory mapped Generic timer interfaces */
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#define SYS_CNTCTL_BASE 0x2a430000
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