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refactor(drivers/marvell/comphy-3700): rename Digital Loopback Enable register constant 

The register at offset 0x23 is called Digital Loopback Enable, but the
constant is COMPHY_LOOPBACK_REG0, as if there were some LOOPBACK_REG1
register or something, which there is not.

Rename the constant to COMPHY_DIG_LOOPBACK_EN.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie88bdd864e2c9ab7e8de70ed7f3a13ee8f08ff79
This commit is contained in:
Marek Behún 2021-12-07 23:59:30 +01:00
parent 95c26d6489
commit 4c995d2d1b
2 changed files with 9 additions and 7 deletions
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11
drivers/marvell/comphy/phy-comphy-3700.c
View File

@ -315,7 +315,7 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
RXD_INVERT_BIT);
/* 1. Select 40-bit data width width */
offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET;
offset = COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET;
comphy_sata_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT,
SEL_DATA_WIDTH_MASK);
@ -352,7 +352,7 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
/* Polling status */
mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET,
COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET);
COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET);
ret = polling_with_timeout(comphy_indir_regs +
COMPHY_LANE2_INDIR_DATA_OFFSET,
@ -477,7 +477,8 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
*/
data = DATA_WIDTH_10BIT;
mask = SEL_DATA_WIDTH_MASK;
reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask);
reg_set16(SGMIIPHY_ADDR(COMPHY_DIG_LOOPBACK_EN, sd_ip_addr),
data, mask);
/*
* 12. As long as DFE function needs to be enabled in any mode,
@ -737,7 +738,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
/*
* 11. Set 20-bit data width
*/
usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT,
usb3_reg_set(reg_base, COMPHY_DIG_LOOPBACK_EN, DATA_WIDTH_20BIT,
REG_16_BIT_MASK);
/*
@ -1025,7 +1026,7 @@ static int mvebu_a3700_comphy_sata_is_pll_locked(void)
/* Polling status */
mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET,
COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET);
COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET);
addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET;
data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT,
COMPHY_PLL_TIMEOUT, REG_32BIT);

5
drivers/marvell/comphy/phy-comphy-3700.h
View File

@ -75,8 +75,9 @@ enum {
#define COMPHY_RESERVED_REG 0x0E
#define PHYCTRL_FRM_PIN_BIT BIT(13)
#define COMPHY_LOOPBACK_REG0 0x23
#define DIG_LB_EN_ADDR(unit) (COMPHY_LOOPBACK_REG0 * PHY_SHFT(unit))
#define COMPHY_DIG_LOOPBACK_EN 0x23
#define DIG_LOOPBACK_EN_ADDR(unit) (COMPHY_DIG_LOOPBACK_EN * \
PHY_SHFT(unit))
#define SEL_DATA_WIDTH_OFFSET 10
#define SEL_DATA_WIDTH_MASK (0x3 << SEL_DATA_WIDTH_OFFSET)
#define DATA_WIDTH_10BIT (0x0 << SEL_DATA_WIDTH_OFFSET)