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Merge "fix(bl1): invalidate SP in data cache during secure SMC" into integration

This commit is contained in:
Madhukar Pappireddy 2022-05-19 21:11:55 +02:00 committed by TrustedFirmware Code Review
parent 70313d363b f1cbbd6332
commit 4cafcc30ed
1 changed files with 9 additions and 1 deletions
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10
bl1/aarch32/bl1_exceptions.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -118,6 +118,14 @@ func smc_handler
mov r0, #DISABLE_DCACHE
bl enable_mmu_svc_mon
/*
* Invalidate `smc_ctx_t` in data cache to prevent dirty data being
* used.
*/
mov r0, r6
mov r1, #SMC_CTX_SIZE
bl inv_dcache_range
/* Enable the data cache. */
ldcopr r9, SCTLR
orr r9, r9, #SCTLR_C_BIT