From f1cbbd6332bb85672dc72cbcc4ac7023323c6936 Mon Sep 17 00:00:00 2001 From: Harrison Mutai Date: Wed, 11 May 2022 11:05:02 +0100 Subject: [PATCH] fix(bl1): invalidate SP in data cache during secure SMC Invalidate the SP holding `smc_ctx_t` prior to enabling the data cache when handling SMCs from the secure world. Enabling the data cache without doing so results in dirty data either being evicted into main memory, or being used directly from bl1. This corrupted data causes system failure as the SMC handler attempts to use it. Change-Id: I5b7225a6fdd1fcfe34ee054ca46dffea06b84b7d Signed-off-by: Harrison Mutai --- bl1/aarch32/bl1_exceptions.S | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/bl1/aarch32/bl1_exceptions.S b/bl1/aarch32/bl1_exceptions.S index 493d2ca4e..4a6815f1f 100644 --- a/bl1/aarch32/bl1_exceptions.S +++ b/bl1/aarch32/bl1_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -118,6 +118,14 @@ func smc_handler mov r0, #DISABLE_DCACHE bl enable_mmu_svc_mon + /* + * Invalidate `smc_ctx_t` in data cache to prevent dirty data being + * used. + */ + mov r0, r6 + mov r1, #SMC_CTX_SIZE + bl inv_dcache_range + /* Enable the data cache. */ ldcopr r9, SCTLR orr r9, r9, #SCTLR_C_BIT