From 4d5d98c77c0c3276cf6b9f39e6efbf5eccf44d6c Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 27 Sep 2016 18:19:30 -0700 Subject: [PATCH] rockchip: fixes the clock select and divide register for rk3399 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON register. As the CRU_CLKSEL_CON96～107 high 16-bit isn't write mask and the CRU_CLKSEL_CON offset is 0x100,not 0x80. Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529 --- plat/rockchip/rk3399/drivers/soc/soc.c | 13 ++++++++++--- plat/rockchip/rk3399/drivers/soc/soc.h | 2 +- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c index 29bf6dda3..6af7a2e23 100644 --- a/plat/rockchip/rk3399/drivers/soc/soc.c +++ b/plat/rockchip/rk3399/drivers/soc/soc.c @@ -325,9 +325,16 @@ void plls_resume_finish(void) { int i; - for (i = 0; i < CRU_CLKSEL_COUNT; i++) - mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)), - REG_SOC_WMSK | slp_data.cru_clksel_con[i]); + for (i = 0; i < CRU_CLKSEL_COUNT; i++) { + /* CRU_CLKSEL_CON96~107 the high 16-bit isb't write_mask */ + if (i > 95) + mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)), + slp_data.cru_clksel_con[i]); + else + mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)), + REG_SOC_WMSK | + slp_data.cru_clksel_con[i]); + } for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) mmio_write_32((PMUCRU_BASE + PMUCRU_CLKSEL_OFFSET + i * REG_SIZE), diff --git a/plat/rockchip/rk3399/drivers/soc/soc.h b/plat/rockchip/rk3399/drivers/soc/soc.h index 906452a38..d99b380ef 100644 --- a/plat/rockchip/rk3399/drivers/soc/soc.h +++ b/plat/rockchip/rk3399/drivers/soc/soc.h @@ -65,7 +65,7 @@ #define PLL_CON_COUNT 0x06 #define CRU_CLKSEL_COUNT 0x108 -#define CRU_CLKSEL_CON(n) (0x80 + (n) * 4) +#define CRU_CLKSEL_CON(n) (0x100 + (n) * 4) #define PMUCRU_CLKSEL_CONUT 0x06 #define PMUCRU_CLKSEL_OFFSET 0x080