intel: agilex: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
This commit is contained in:
Hadi Asyrafi
parent
5119fa7b8d
commit
4e865bd290
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@ -69,9 +69,9 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
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deassert_peripheral_reset();
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config_hps_hs_before_warm_reset();
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watchdog_init(get_wdt_clk(&reverse_handoff_ptr));
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watchdog_init(get_wdt_clk());
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console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
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console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE,
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&console);
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socfpga_delay_timer_init();
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@ -105,7 +105,7 @@ void bl2_el3_plat_arch_setup(void)
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enable_mmu_el3(0);
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dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000);
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dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
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info.mmc_dev_type = MMC_IS_SD;
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info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
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@ -80,41 +80,38 @@
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#define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000) >> 16)
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#define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004
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#define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008
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#define CLKMGR_INTOSC_HZ 460000000
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/* Main PLL Macros */
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#define CLKMGR_MAINPLL_EN_RESET 0x000000ff
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#define CLKMGR_MAINPLL_PLLM_MDIV(x) ((x) & 0x000003ff)
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#define CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK 0x00000001
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#define CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK 0x00000002
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#define CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
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#define CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8)
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#define CLKMGR_MAINPLL_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12)
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#define CLKMGR_MAINPLL_PLLGLOB_PSRC(x) (((x) & 0x00030000) >> 16)
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#define CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1 0x0
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#define CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC 0x1
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#define CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S 0x2
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#define CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff)
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#define CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000)
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/* Peripheral PLL Macros */
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#define CLKMGR_PERPLL_EN_RESET 0x00000fff
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#define CLKMGR_PERPLL_PLLM_MDIV(x) ((x) & 0x000003ff)
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#define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff)
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#define CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK 0x00000001
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#define CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
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#define CLKMGR_PERPLL_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8)
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#define CLKMGR_PERPLL_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12)
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#define CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK 0x00000002
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#define CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff)
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#define CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000)
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/* Altera Macros */
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#define CLKMGR_ALTERA_EXTCNTRST_RESET 0xff
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/* Shared Macros */
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#define CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16)
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#define CLKMGR_PSRC_MAIN 0
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#define CLKMGR_PSRC_PER 1
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#define CLKMGR_PLLGLOB_PSRC_EOSC1 0x0
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#define CLKMGR_PLLGLOB_PSRC_INTOSC 0x1
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#define CLKMGR_PLLGLOB_PSRC_F2S 0x2
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#define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003ff)
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#define CLKMGR_PLLGLOB_PD_SET_MSK 0x00000001
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#define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002
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#define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
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#define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8)
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#define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12)
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#define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff)
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#define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000)
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typedef struct {
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uint32_t clk_freq_of_eosc1;
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@ -123,6 +120,8 @@ typedef struct {
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} CLOCK_SOURCE_CONFIG;
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void config_clkmgr_handoff(handoff *hoff_ptr);
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int get_wdt_clk(handoff *hoff_ptr);
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uint32_t get_wdt_clk(void);
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uint32_t get_uart_clk(void);
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uint32_t get_mmc_clk(void);
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#endif
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@ -11,14 +11,13 @@
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#define AGX_MMC_REG_BASE 0xff808000
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#define EMMC_DESC_SIZE (1<<20)
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#define EMMC_INIT_PARAMS(base) \
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#define EMMC_INIT_PARAMS(base, clk) \
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{ .bus_width = MMC_BUS_WIDTH_4, \
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.clk_rate = 50000000, \
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.clk_rate = (clk), \
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.desc_base = (base), \
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.desc_size = EMMC_DESC_SIZE, \
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.flags = 0, \
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.reg_base = AGX_MMC_REG_BASE, \
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\
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.reg_base = AGX_MMC_REG_BASE \
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}
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typedef enum {
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@ -26,7 +25,7 @@ typedef enum {
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BOOT_SOURCE_SDMMC,
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BOOT_SOURCE_NAND,
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BOOT_SOURCE_RSVD,
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BOOT_SOURCE_QSPI,
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BOOT_SOURCE_QSPI
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} boot_source_type;
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void enable_nonsecure_access(void);
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@ -65,6 +65,11 @@
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#define AGX_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
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#define AGX_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
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#define AGX_SYSMGR_CORE(x) (0xffd12000 + (x))
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#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
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#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
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#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
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#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
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#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
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@ -12,15 +12,8 @@
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#include "agilex_clock_manager.h"
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#include "agilex_handoff.h"
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#include "agilex_system_manager.h"
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static const CLOCK_SOURCE_CONFIG clk_source = {
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/* clk_freq_of_eosc1 */
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(uint32_t) 25000000,
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/* clk_freq_of_f2h_free */
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(uint32_t) 400000000,
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/* clk_freq_of_cb_intosc_ls */
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(uint32_t) 50000000,
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};
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uint32_t wait_pll_lock(void)
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{
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@ -114,18 +107,18 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
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/* Put both PLL in reset and power down */
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mmio_clrbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
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CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK |
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CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK);
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CLKMGR_PLLGLOB_PD_SET_MSK |
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CLKMGR_PLLGLOB_RST_SET_MSK);
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mmio_clrbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB,
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CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK |
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CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK);
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CLKMGR_PLLGLOB_PD_SET_MSK |
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CLKMGR_PLLGLOB_RST_SET_MSK);
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/* Setup main PLL dividers */
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mdiv = CLKMGR_MAINPLL_PLLM_MDIV(hoff_ptr->main_pll_pllm);
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mdiv = CLKMGR_PLLM_MDIV(hoff_ptr->main_pll_pllm);
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arefclk_div = CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(
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arefclk_div = CLKMGR_PLLGLOB_AREFCLKDIV(
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hoff_ptr->main_pll_pllglob);
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drefclk_div = CLKMGR_MAINPLL_PLLGLOB_DREFCLKDIV(
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drefclk_div = CLKMGR_PLLGLOB_DREFCLKDIV(
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hoff_ptr->main_pll_pllglob);
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mscnt = 100 / (mdiv / BIT(drefclk_div));
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@ -134,8 +127,8 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
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hscnt = (mdiv * mscnt * BIT(drefclk_div) / arefclk_div) - 4;
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_VCOCALIB,
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CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(hscnt) |
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CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(mscnt));
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CLKMGR_VCOCALIB_HSCNT_SET(hscnt) |
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CLKMGR_VCOCALIB_MSCNT_SET(mscnt));
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mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV,
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hoff_ptr->main_pll_nocdiv);
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@ -159,11 +152,11 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
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hoff_ptr->main_pll_nocclk);
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/* Setup peripheral PLL dividers */
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mdiv = CLKMGR_PERPLL_PLLM_MDIV(hoff_ptr->per_pll_pllm);
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mdiv = CLKMGR_PLLM_MDIV(hoff_ptr->per_pll_pllm);
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arefclk_div = CLKMGR_PERPLL_PLLGLOB_AREFCLKDIV(
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arefclk_div = CLKMGR_PLLGLOB_AREFCLKDIV(
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hoff_ptr->per_pll_pllglob);
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drefclk_div = CLKMGR_PERPLL_PLLGLOB_DREFCLKDIV(
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drefclk_div = CLKMGR_PLLGLOB_DREFCLKDIV(
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hoff_ptr->per_pll_pllglob);
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mscnt = 100 / (mdiv / BIT(drefclk_div));
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@ -172,8 +165,8 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
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hscnt = (mdiv * mscnt * BIT(drefclk_div) / arefclk_div) - 4;
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_VCOCALIB,
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CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(hscnt) |
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CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(mscnt));
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CLKMGR_VCOCALIB_HSCNT_SET(hscnt) |
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CLKMGR_VCOCALIB_MSCNT_SET(mscnt));
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EMACCTL,
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hoff_ptr->per_pll_emacctl);
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@ -197,11 +190,11 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
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/* Take both PLL out of reset and power up */
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mmio_setbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
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CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK |
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CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK);
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CLKMGR_PLLGLOB_PD_SET_MSK |
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CLKMGR_PLLGLOB_RST_SET_MSK);
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mmio_setbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB,
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CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK |
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CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK);
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CLKMGR_PLLGLOB_PD_SET_MSK |
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CLKMGR_PLLGLOB_RST_SET_MSK);
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wait_pll_lock();
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@ -256,24 +249,31 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
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CLKMGR_MAINPLL_EN_RESET);
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mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN,
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CLKMGR_PERPLL_EN_RESET);
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/* Pass clock source frequency into scratch register */
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mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1),
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hoff_ptr->hps_osc_clk_h);
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mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2),
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hoff_ptr->fpga_clk_hz);
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}
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int get_wdt_clk(handoff *hoff_ptr)
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/* Extract reference clock from platform clock source */
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uint32_t get_ref_clk(uint32_t pllglob)
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{
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int main_noc_base_clk, l3_main_free_clk, l4_sys_free_clk;
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int data32, mdiv, arefclkdiv, ref_clk;
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uint32_t arefclkdiv, ref_clk;
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uint32_t scr_reg;
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data32 = mmio_read_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB);
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switch (CLKMGR_MAINPLL_PLLGLOB_PSRC(data32)) {
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case CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1:
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ref_clk = clk_source.clk_freq_of_eosc1;
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switch (CLKMGR_PSRC(pllglob)) {
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case CLKMGR_PLLGLOB_PSRC_EOSC1:
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scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1);
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ref_clk = mmio_read_32(scr_reg);
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break;
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case CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC:
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ref_clk = clk_source.clk_freq_of_cb_intosc_ls;
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case CLKMGR_PLLGLOB_PSRC_INTOSC:
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ref_clk = CLKMGR_INTOSC_HZ;
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break;
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case CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S:
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ref_clk = clk_source.clk_freq_of_f2h_free;
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case CLKMGR_PLLGLOB_PSRC_F2S:
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scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2);
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ref_clk = mmio_read_32(scr_reg);
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break;
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default:
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ref_clk = 0;
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@ -281,13 +281,91 @@ int get_wdt_clk(handoff *hoff_ptr)
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break;
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}
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arefclkdiv = CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(data32);
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mdiv = CLKMGR_MAINPLL_PLLM_MDIV(hoff_ptr->main_pll_pllm);
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arefclkdiv = CLKMGR_PLLGLOB_AREFCLKDIV(pllglob);
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ref_clk /= arefclkdiv;
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ref_clk = (ref_clk / arefclkdiv) * mdiv;
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main_noc_base_clk = ref_clk / (hoff_ptr->main_pll_pllc1 & 0x7ff);
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l3_main_free_clk = main_noc_base_clk / (hoff_ptr->main_pll_nocclk + 1);
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l4_sys_free_clk = l3_main_free_clk / 4;
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return l4_sys_free_clk;
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return ref_clk;
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}
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/* Calculate clock frequency based on parameter */
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uint32_t get_clk_freq(uint32_t psrc_reg, uint32_t main_pllc, uint32_t per_pllc)
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{
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uint32_t clk_psrc, mdiv, ref_clk;
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uint32_t pllm_reg, pllc_reg, pllc_div, pllglob_reg;
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clk_psrc = mmio_read_32(CLKMGR_MAINPLL + psrc_reg);
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switch (CLKMGR_PSRC(clk_psrc)) {
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case CLKMGR_PSRC_MAIN:
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pllm_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLM;
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pllc_reg = CLKMGR_MAINPLL + main_pllc;
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pllglob_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB;
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break;
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case CLKMGR_PSRC_PER:
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pllm_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLM;
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pllc_reg = CLKMGR_PERPLL + per_pllc;
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pllglob_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB;
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break;
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default:
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return 0;
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}
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ref_clk = get_ref_clk(mmio_read_32(pllglob_reg));
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mdiv = CLKMGR_PLLM_MDIV(mmio_read_32(pllm_reg));
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ref_clk *= mdiv;
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pllc_div = mmio_read_32(pllc_reg) & 0x7ff;
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return ref_clk / pllc_div;
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}
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/* Return L3 interconnect clock */
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uint32_t get_l3_clk(void)
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{
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uint32_t l3_clk;
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l3_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC1,
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CLKMGR_PERPLL_PLLC1);
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return l3_clk;
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}
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/* Calculate clock frequency to be used for watchdog timer */
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uint32_t get_wdt_clk(void)
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{
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uint32_t l3_clk, l4_sys_clk;
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l3_clk = get_l3_clk();
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l4_sys_clk = l3_clk / 4;
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return l4_sys_clk;
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}
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/* Calculate clock frequency to be used for UART driver */
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uint32_t get_uart_clk(void)
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{
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uint32_t data32, l3_clk, l4_sp_clk;
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l3_clk = get_l3_clk();
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data32 = mmio_read_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV);
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data32 = (data32 >> 16) & 0x3;
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l4_sp_clk = l3_clk >> data32;
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return l4_sp_clk;
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}
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/* Calculate clock frequency to be used for SDMMC driver */
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uint32_t get_mmc_clk(void)
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{
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uint32_t data32, mmc_clk;
|
||||
|
||||
mmc_clk = get_clk_freq(CLKMGR_ALTERA_SDMMCCTR,
|
||||
CLKMGR_MAINPLL_PLLC3, CLKMGR_PERPLL_PLLC3);
|
||||
|
||||
data32 = mmio_read_32(CLKMGR_ALTERA + CLKMGR_ALTERA_SDMMCCTR);
|
||||
data32 = (data32 & 0x7ff) + 1;
|
||||
mmc_clk = (mmc_clk / data32) / 4;
|
||||
|
||||
return mmc_clk;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue