From 4ea8dc4e02ce3b9f37b10950e650f6dda222b782 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Thu, 4 Aug 2016 20:46:35 +0800 Subject: [PATCH] rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5 The default value of L2CTLR_DATA_RAM_LATENCY is 2, depends to the test result on rk3399, the A72 will need lower voltage for high frequency if it's set to be 5, and almost no effect on performance. Change-Id: I99a6a43edcc0c58f7775c10f4b85669dc3eff66d Signed-off-by: Caesar Wang --- plat/rockchip/common/aarch64/plat_helpers.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S index d06d4cbaa..a93b526f8 100644 --- a/plat/rockchip/common/aarch64/plat_helpers.S +++ b/plat/rockchip/common/aarch64/plat_helpers.S @@ -67,7 +67,7 @@ handler_a72: * Set the L2 Data RAM latency for Cortex-A72. * Set the L2 Tag RAM latency to for Cortex-A72. */ - mov x0, #((2 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ + mov x0, #((5 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ (0x1 << 5)) msr L2CTLR_EL1, x0 isb