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drivers/marvell: check if TRNG unit is present 

Some Marvell SoCs may have crypto engine disabled in the HW.
This patch checks the AP LD0 efuse for crypto engine/TRNG
presence before initializing the driver.

Change-Id: I441e7c69a137106bd36302b028b04c0b31896dbd
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47314
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
This commit is contained in:
Konstantin Porotchkin 2021-03-07 13:48:21 +02:00 committed by Manish Pandey
parent 90eac1703d
commit 4eb72fe921
1 changed files with 19 additions and 0 deletions
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19
drivers/marvell/mochi/cp110_setup.c
View File

@ -14,6 +14,7 @@
#include <drivers/marvell/mochi/cp110_setup.h>
#include <drivers/rambus/trng_ip_76.h>
#include <efuse_def.h>
#include <plat_marvell.h>
/*
@ -110,6 +111,8 @@
* TRNG Configuration
******************************************************************************/
#define MVEBU_TRNG_BASE (0x760000)
#define MVEBU_EFUSE_TRNG_ENABLE_EFUSE_WORD MVEBU_AP_LDX_220_189_EFUSE_OFFS
#define MVEBU_EFUSE_TRNG_ENABLE_BIT_OFFSET 13 /* LD0[202] */
enum axi_attr {
AXI_ADUNIT_ATTR = 0,
@ -389,6 +392,22 @@ static void cp110_trng_init(uintptr_t base)
{
static bool done;
int ret;
uint32_t reg_val, efuse;
/* Set access to LD0 */
reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG);
reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK;
mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val);
/* Obtain the AP LD0 bit defining TRNG presence */
efuse = mmio_read_32(MVEBU_EFUSE_TRNG_ENABLE_EFUSE_WORD);
efuse >>= MVEBU_EFUSE_TRNG_ENABLE_BIT_OFFSET;
efuse &= 1;
if (efuse == 0) {
VERBOSE("TRNG is not present, skipping");
return;
}
if (!done) {
ret = eip76_rng_probe(base + MVEBU_TRNG_BASE);