Add documentation for SMMUv3 driver in Hafnium(SPM)
Change-Id: I0b38c114fd2958d2b4040585611cafa132ccfd9c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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@ -6,6 +6,8 @@ Secure Partition Manager
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Acronyms
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Acronyms
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========
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========
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+--------+-----------------------------------+
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| DMA | Direct Memory Access |
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+--------+-----------------------------------+
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+--------+-----------------------------------+
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| DTB | Device Tree Blob |
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| DTB | Device Tree Blob |
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+--------+-----------------------------------+
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+--------+-----------------------------------+
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@ -33,6 +35,8 @@ Acronyms
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+--------+-----------------------------------+
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+--------+-----------------------------------+
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| PSA | Platform Security Architecture |
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| PSA | Platform Security Architecture |
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+--------+-----------------------------------+
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+--------+-----------------------------------+
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| SMMU | System Memory Management Unit |
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+--------+-----------------------------------+
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| SP | Secure Partition |
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| SP | Secure Partition |
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+--------+-----------------------------------+
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+--------+-----------------------------------+
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| SPM | Secure Partition Manager |
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| SPM | Secure Partition Manager |
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@ -832,6 +836,114 @@ The register operation can either be an implementation-defined service call
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to the SPMC when the primary SP EC boots, or be supplied through the SP
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to the SPMC when the primary SP EC boots, or be supplied through the SP
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manifest.
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manifest.
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Support for SMMUv3 in Hafnium
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=============================
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An SMMU is analogous to an MMU in a CPU. It performs address translations for
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Direct Memory Access (DMA) requests from system I/O devices.
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The responsibilities of an SMMU include:
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- Translation: Incoming DMA requests are translated from bus address space to
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system physical address space using translation tables compliant to
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Armv8/Armv7 VMSA descriptor format.
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- Protection: An I/O device can be prohibited from read, write access to a
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memory region or allowed.
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- Isolation: Traffic from each individial device can be independently managed.
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The devices are differentiated from each other using unique translation
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tables.
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The following diagram illustrates a typical SMMU IP integrated in a SoC with
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several I/O devices along with Interconnect and Memory system.
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.. image:: ../resources/diagrams/MMU-600.png
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SMMU has several versions including SMMUv1, SMMUv2 and SMMUv3. Hafnium provides
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support for SMMUv3 driver in both Normal and Secure World. A brief introduction
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of SMMUv3 functionality and the corresponding software support in Hafnium is
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provided here.
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SMMUv3 features
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---------------
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- SMMUv3 provides Stage1, Stage2 translation as well as nested (Stage1 + Stage2)
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translation support. It can either bypass or abort incoming translations as
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well.
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- Traffic (memory transactions) from each upstream I/O peripheral device,
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referred to as Stream, can be independently managed using a combination of
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several memory based configuration structures. This allows the SMMUv3 to
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support a large number of streams with each stream assigned to a unique
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translation context.
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- Support for Armv8.1 VMSA where the SMMU shares the translation tables with
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a Processing Element. AArch32(LPAE) and AArch64 translation table format
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are supported by SMMUv3.
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- SMMUv3 offers non-secure stream support with secure stream support being
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optional. Logically, SMMUv3 behaves as if there is an indepdendent SMMU
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instance for secure and non-secure stream support.
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- It also supports sub-streams to differentiate traffic from a virtualized
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peripheral associated with a VM/SP.
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- Additionally, SMMUv3.2 provides support for PEs implementing Armv8.4-A
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extensions. Consequently, SPM depends on Secure EL2 support in SMMUv3.2
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for providing Secure Stage2 translation support to upstream peripheral
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devices.
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SMMUv3 Programming Interfaces
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-----------------------------
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SMMUv3 has three software interfaces that are used by the Hafnium driver to
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configure the behaviour of SMMUv3 and manage the streams.
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- Memory based data strutures that provide unique translation context for
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each stream.
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- Memory based circular buffers for command queue and event queue.
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- A large number of SMMU configuration registers that are memory mapped during
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boot time by Hafnium driver. Except a few registers, all configuration
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registers have independent secure and non-secure versions to configure the
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behaviour of SMMUv3 for translation of secure and non-secure streams
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respectively.
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Peripheral device manifest
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--------------------------
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Currently, SMMUv3 driver in Hafnium only supports dependent peripheral devices.
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These devices are dependent on PE endpoint to initiate and receive memory
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management transactions on their behalf. The acccess to the MMIO regions of
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any such device is assigned to the endpoint during boot. Moreover, SMMUv3 driver
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uses the same stage 2 translations for the device as those used by partition
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manager on behalf of the PE endpoint. This ensures that the peripheral device
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has the same visibility of the physical address space as the endpoint. The
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device node of the corresponding partition manifest (refer to `[1]`_ section 3.2
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) must specify these additional properties for each peripheral device in the
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system :
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- smmu-id: This field helps to identify the SMMU instance that this device is
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upstream of.
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- stream-ids: List of stream IDs assigned to this device.
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.. code:: shell
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smmuv3-testengine {
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base-address = <0x00000000 0x2bfe0000>;
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pages-count = <32>;
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attributes = <0x3>;
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smmu-id = <0>;
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stream-ids = <0x0 0x1>;
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interrupts = <0x2 0x3>, <0x4 0x5>;
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exclusive-access;
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};
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SMMUv3 driver limitations
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-------------------------
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The primary design goal for the Hafnium SMMU driver is to support secure
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streams.
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- Currently, the driver only supports Stage2 translations. No support for
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Stage1 or nested translations.
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- Supports only AArch64 translation format.
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- No support for features such as PCI Express (PASIDs, ATS, PRI), MSI, RAS,
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Fault handling, Performance Monitor Extensions, Event Handling, MPAM.
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- No support for independent peripheral devices.
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References
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References
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==========
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==========
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