plat/arm/tzc: add support to configure multiple tzc400

For platforms that have two or more TZC400 controllers instantiated,
allow the TZC400 driver to be usable with all those instances.
This is achieved by allowing 'arm_tzc400_setup' function to accept
the base address of the TZC400 controller.

Change-Id: I4add470e6ddb58432cd066145e644112400ab924
Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>
This commit is contained in:
Suyash Pathak 2020-02-04 13:55:20 +05:30
parent 86f297a3e1
commit 4ed1676518
4 changed files with 12 additions and 10 deletions

View File

@ -152,7 +152,8 @@ void arm_setup_romlib(void);
int arm_io_setup(void);
/* Security utility functions */
void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions);
void arm_tzc400_setup(uintptr_t tzc_base,
const arm_tzc_regions_info_t *tzc_regions);
struct tzc_dmc500_driver_data;
void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data,
const arm_tzc_regions_info_t *tzc_regions);

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -22,5 +22,5 @@ void plat_arm_security_setup(void)
*/
if ((get_arm_config()->flags & ARM_CONFIG_HAS_TZC) != 0U)
arm_tzc400_setup(NULL);
arm_tzc400_setup(PLAT_ARM_TZC_BASE, NULL);
}

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -127,13 +127,13 @@ void plat_arm_security_setup(void)
init_debug_cfg();
/* Initialize the TrustZone Controller */
#ifdef JUNO_TZMP1
arm_tzc400_setup(juno_tzmp1_tzc_regions);
arm_tzc400_setup(PLAT_ARM_TZC_BASE, juno_tzmp1_tzc_regions);
INFO("TZC protected shared memory base address for TZMP usecase: %p\n",
(void *)JUNO_AP_TZC_SHARE_DRAM1_BASE);
INFO("TZC protected shared memory end address for TZMP usecase: %p\n",
(void *)JUNO_AP_TZC_SHARE_DRAM1_END);
#else
arm_tzc400_setup(NULL);
arm_tzc400_setup(PLAT_ARM_TZC_BASE, NULL);
#endif
/* Do ARM CSS internal NIC setup */
css_init_nic400();

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -19,7 +19,8 @@
* When booting an EL3 payload, this is simplified: we configure region 0 with
* secure access only and do not enable any other region.
******************************************************************************/
void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions)
void arm_tzc400_setup(uintptr_t tzc_base,
const arm_tzc_regions_info_t *tzc_regions)
{
#ifndef EL3_PAYLOAD_BASE
unsigned int region_index = 1U;
@ -32,7 +33,7 @@ void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions)
INFO("Configuring TrustZone Controller\n");
tzc400_init(PLAT_ARM_TZC_BASE);
tzc400_init(tzc_base);
/* Disable filters. */
tzc400_disable_filters();
@ -74,5 +75,5 @@ void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions)
void plat_arm_security_setup(void)
{
arm_tzc400_setup(NULL);
arm_tzc400_setup(PLAT_ARM_TZC_BASE, NULL);
}