Do not trap access to floating point registers
Traps when accessing architectural features are disabled by clearing bits in CPTR_EL3 during early boot, including accesses to floating point registers. The value of this register was previously undetermined, causing unwanted traps to EL3. Future EL3 code (for example, context save/restore code) may use floating point registers, although they are not used by current code. Also, the '-mgeneral-regs-only' flag is enabled in the GCC settings to prevent generation of code that uses floating point registers. Change-Id: I9a03675f6387bbbee81a6f2c9ccf81150db03747
This commit is contained in:
Harry Liebel
Dan Handley
parent
e83b0cadc6
commit
4f6036834f
7
Makefile
7
Makefile
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@ -97,9 +97,10 @@ INCLUDES += -Ilib/include/ -Iinclude/aarch64/ -Iinclude/ \
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-Iinclude/stdlib -Iinclude/stdlib/sys
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ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \
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-D__ASSEMBLY__ ${INCLUDES}
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CFLAGS := -nostdinc -pedantic -ffreestanding -Wall -Werror \
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-std=c99 -c -Os -DDEBUG=${DEBUG} ${INCLUDES} ${CFLAGS}
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-mgeneral-regs-only -D__ASSEMBLY__ ${INCLUDES}
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CFLAGS := -nostdinc -pedantic -ffreestanding -Wall \
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-Werror -mgeneral-regs-only -std=c99 -c -Os \
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-DDEBUG=${DEBUG} ${INCLUDES} ${CFLAGS}
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LDFLAGS += --fatal-warnings -O1
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BL1_LDFLAGS := -Map=${BL1_MAPFILE} --script ${BL1_LINKERFILE} --entry=${BL1_ENTRY_POINT}
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@ -61,9 +61,6 @@ void bl1_arch_setup(void)
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enable_serror();
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enable_debug_exceptions();
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/* Do not trap coprocessor accesses from lower ELs to EL3 */
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write_cptr_el3(0);
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/* Read the frequency from Frequency modes table */
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counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
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/* The first entry of the frequency modes table must not be 0 */
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@ -57,6 +57,29 @@ reset_handler:; .type reset_handler, %function
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adr x0, early_exceptions
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msr vbar_el3, x0
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/* ---------------------------------------------------------------------
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* The initial state of the Architectural feature trap register
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* (CPTR_EL3) is unknown and it must be set to a known state. All
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* feature traps are disabled. Some bits in this register are marked as
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* Reserved and should not be modified.
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*
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* CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
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* or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
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* CPTR_EL3.TTA: This causes access to the Trace functionality to trap
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* to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
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* access to trace functionality is not supported, this bit is RES0.
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* CPTR_EL3.TFP: This causes instructions that access the registers
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* associated with Floating Point and Advanced SIMD execution to trap
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* to EL3 when executed from any exception level, unless trapped to EL1
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* or EL2.
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* ---------------------------------------------------------------------
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*/
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mrs x0, cptr_el3
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bic w0, w0, #TCPAC_BIT
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bic w0, w0, #TTA_BIT
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bic w0, w0, #TFP_BIT
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msr cptr_el3, x0
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/* ---------------------------------------------
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* Enable the instruction cache.
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* ---------------------------------------------
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@ -62,9 +62,6 @@ void bl31_arch_setup(void)
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enable_serror();
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enable_debug_exceptions();
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/* Do not trap coprocessor accesses from lower ELs to EL3 */
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write_cptr_el3(0);
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/* Read the frequency from Frequency modes table */
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counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
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/* The first entry of the frequency modes table must not be 0 */
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@ -61,6 +61,29 @@ bl31_entrypoint:; .type bl31_entrypoint, %function
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adr x1, runtime_exceptions
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msr vbar_el3, x1
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/* ---------------------------------------------------------------------
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* The initial state of the Architectural feature trap register
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* (CPTR_EL3) is unknown and it must be set to a known state. All
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* feature traps are disabled. Some bits in this register are marked as
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* Reserved and should not be modified.
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*
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* CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
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* or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
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* CPTR_EL3.TTA: This causes access to the Trace functionality to trap
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* to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
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* access to trace functionality is not supported, this bit is RES0.
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* CPTR_EL3.TFP: This causes instructions that access the registers
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* associated with Floating Point and Advanced SIMD execution to trap
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* to EL3 when executed from any exception level, unless trapped to EL1
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* or EL2.
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* ---------------------------------------------------------------------
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*/
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mrs x1, cptr_el3
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bic w1, w1, #TCPAC_BIT
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bic w1, w1, #TTA_BIT
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bic w1, w1, #TFP_BIT
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msr cptr_el3, x1
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/* ---------------------------------------------
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* Enable the instruction cache.
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* ---------------------------------------------
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@ -89,6 +89,11 @@ Detailed changes since last release
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separate issue tracking repository
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https://github.com/ARM-software/tf-issues.
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* Cleared bits in the architectural trap feature register (CPTR_EL3) during
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early boot to prevent traps when accessing certain registers, including
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floating point registers. Also added `-mgeneral-regs-only` flag to GCC
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settings to prevent generation of code using floating point registers.
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ARM Trusted Firmware - version 0.2
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==================================
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@ -672,11 +672,13 @@ BL1 performs minimal architectural initialization as follows.
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Aborts and SError Interrupts are configured to be taken in EL3 by
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setting the `SCR.EA` bit.
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- `CPTR_EL3`. Accesses to the `CPACR` from EL1 or EL2, or the `CPTR_EL2`
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from EL2 are configured to not trap to EL3 by clearing the
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`CPTR_EL3.TCPAC` bit. Instructions that access the registers associated
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with Floating Point and Advanced SIMD execution are configured to not
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trap to EL3 by clearing the `CPTR_EL3.TFP` bit.
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- `CPTR_EL3`. Accesses to the `CPACR_EL1` register from EL1 or EL2, or the
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`CPTR_EL2` register from EL2 are configured to not trap to EL3 by
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clearing the `CPTR_EL3.TCPAC` bit. Access to the trace functionality is
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configured not to trap to EL3 by clearing the `CPTR_EL3.TTA` bit.
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Instructions that access the registers associated with Floating Point
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and Advanced SIMD execution are configured to not trap to EL3 by
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clearing the `CPTR_EL3.TFP` bit.
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- `CNTFRQ_EL0`. The `CNTFRQ_EL0` register is programmed with the base
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frequency of the system counter, which is retrieved from the first entry
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@ -167,7 +167,8 @@
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#define EL0VCTEN_BIT (1 << 1)
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/* CPTR_EL3 definitions */
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#define TCPAC_BIT (1ull << 31)
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#define TCPAC_BIT (1 << 31)
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#define TTA_BIT (1 << 20)
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#define TFP_BIT (1 << 10)
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/* CPSR/SPSR definitions */
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