Merge pull request #1712 from jeenu-arm/ssbs
AArch64: Use SSBS for CVE_2018_3639 mitigation
This commit is contained in:
Soby Mathew
GitHub
commit
4f7812e7ac
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@ -177,9 +177,13 @@
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*
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* SCTLR.V: Set to zero to select the normal exception vectors
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* with base address held in VBAR.
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*
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* SCTLR.DSSBS: Set to zero to disable speculation store bypass
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* safe behaviour upon exception entry to EL3.
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* -------------------------------------------------------------
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*/
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ldr r0, =(SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_EE_BIT | SCTLR_V_BIT))
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ldr r0, =(SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_EE_BIT | \
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SCTLR_V_BIT | SCTLR_DSSBS_BIT))
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stcopr r0, SCTLR
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isb
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.endif /* _init_sctlr */
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@ -194,10 +194,13 @@
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* SCTLR_EL3.SA: Set to zero to disable Stack Alignment check.
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*
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* SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
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*
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* SCTLR.DSSBS: Set to zero to disable speculation store bypass
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* safe behaviour upon exception entry to EL3.
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* -------------------------------------------------------------
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*/
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mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
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| SCTLR_SA_BIT | SCTLR_A_BIT))
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| SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT))
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msr sctlr_el3, x0
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isb
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.endif /* _init_sctlr */
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@ -132,6 +132,7 @@
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#define SCTLR_TRE_BIT (U(1) << 28)
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#define SCTLR_AFE_BIT (U(1) << 29)
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#define SCTLR_TE_BIT (U(1) << 30)
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#define SCTLR_DSSBS_BIT (U(1) << 31)
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#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \
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SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
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@ -198,6 +198,12 @@
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#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
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#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
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/* ID_AA64PFR1_EL1 definitions */
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#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
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#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
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#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
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/* ID_PFR1_EL1 definitions */
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#define ID_PFR1_VIRTEXT_SHIFT U(12)
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#define ID_PFR1_VIRTEXT_MASK U(0xf)
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@ -219,29 +225,30 @@
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(U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
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(U(1) << 11) | (U(1) << 5) | (U(1) << 4))
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#define SCTLR_M_BIT (U(1) << 0)
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#define SCTLR_A_BIT (U(1) << 1)
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#define SCTLR_C_BIT (U(1) << 2)
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#define SCTLR_SA_BIT (U(1) << 3)
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#define SCTLR_SA0_BIT (U(1) << 4)
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#define SCTLR_CP15BEN_BIT (U(1) << 5)
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#define SCTLR_ITD_BIT (U(1) << 7)
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#define SCTLR_SED_BIT (U(1) << 8)
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#define SCTLR_UMA_BIT (U(1) << 9)
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#define SCTLR_I_BIT (U(1) << 12)
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#define SCTLR_V_BIT (U(1) << 13)
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#define SCTLR_DZE_BIT (U(1) << 14)
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#define SCTLR_UCT_BIT (U(1) << 15)
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#define SCTLR_NTWI_BIT (U(1) << 16)
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#define SCTLR_NTWE_BIT (U(1) << 18)
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#define SCTLR_WXN_BIT (U(1) << 19)
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#define SCTLR_UWXN_BIT (U(1) << 20)
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#define SCTLR_E0E_BIT (U(1) << 24)
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#define SCTLR_EE_BIT (U(1) << 25)
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#define SCTLR_UCI_BIT (U(1) << 26)
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#define SCTLR_TRE_BIT (U(1) << 28)
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#define SCTLR_AFE_BIT (U(1) << 29)
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#define SCTLR_TE_BIT (U(1) << 30)
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#define SCTLR_M_BIT (ULL(1) << 0)
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#define SCTLR_A_BIT (ULL(1) << 1)
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#define SCTLR_C_BIT (ULL(1) << 2)
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#define SCTLR_SA_BIT (ULL(1) << 3)
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#define SCTLR_SA0_BIT (ULL(1) << 4)
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#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
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#define SCTLR_ITD_BIT (ULL(1) << 7)
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#define SCTLR_SED_BIT (ULL(1) << 8)
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#define SCTLR_UMA_BIT (ULL(1) << 9)
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#define SCTLR_I_BIT (ULL(1) << 12)
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#define SCTLR_V_BIT (ULL(1) << 13)
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#define SCTLR_DZE_BIT (ULL(1) << 14)
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#define SCTLR_UCT_BIT (ULL(1) << 15)
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#define SCTLR_NTWI_BIT (ULL(1) << 16)
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#define SCTLR_NTWE_BIT (ULL(1) << 18)
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#define SCTLR_WXN_BIT (ULL(1) << 19)
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#define SCTLR_UWXN_BIT (ULL(1) << 20)
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#define SCTLR_E0E_BIT (ULL(1) << 24)
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#define SCTLR_EE_BIT (ULL(1) << 25)
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#define SCTLR_UCI_BIT (ULL(1) << 26)
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#define SCTLR_TRE_BIT (ULL(1) << 28)
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#define SCTLR_AFE_BIT (ULL(1) << 29)
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#define SCTLR_TE_BIT (ULL(1) << 30)
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#define SCTLR_DSSBS_BIT (ULL(1) << 44)
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#define SCTLR_RESET_VAL SCTLR_EL3_RES1
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/* CPACR_El1 definitions */
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@ -208,14 +208,20 @@ endfunc cortex_a76_disable_wa_cve_2018_3639
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func cortex_a76_reset_func
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mov x19, x30
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#if WORKAROUND_CVE_2018_3639
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/* If the PE implements SSBS, we don't need the dynamic workaround */
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mrs x0, id_aa64pfr1_el1
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lsr x0, x0, #ID_AA64PFR1_EL1_SSBS_SHIFT
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and x0, x0, #ID_AA64PFR1_EL1_SSBS_MASK
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cbnz x0, 1f
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mrs x0, CORTEX_A76_CPUACTLR2_EL1
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orr x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
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msr CORTEX_A76_CPUACTLR2_EL1, x0
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isb
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2018_3639
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#ifdef IMAGE_BL31
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/*
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* The Cortex-A76 generic vectors are overwritten to use the vectors
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* defined above. This is required in order to apply mitigation
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@ -226,6 +232,9 @@ func cortex_a76_reset_func
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isb
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#endif
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1:
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#endif
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#if ERRATA_DSU_936184
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bl errata_dsu_936184_wa
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#endif
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@ -30,9 +30,27 @@ static int32_t smccc_arch_features(u_register_t arg)
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return 1;
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return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
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#endif
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#if WORKAROUND_CVE_2018_3639
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case SMCCC_ARCH_WORKAROUND_2:
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case SMCCC_ARCH_WORKAROUND_2: {
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#if DYNAMIC_WORKAROUND_CVE_2018_3639
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unsigned long long ssbs;
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/*
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* Firmware doesn't have to carry out dynamic workaround if the
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* PE implements architectural Speculation Store Bypass Safe
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* (SSBS) feature.
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*/
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ssbs = (read_id_aa64pfr0_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
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ID_AA64PFR1_EL1_SSBS_MASK;
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/*
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* If architectural SSBS is available on this PE, no firmware
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* mitigation via SMCCC_ARCH_WORKAROUND_2 is required.
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*/
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if (ssbs != SSBS_UNAVAILABLE)
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return 1;
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/*
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* On a platform where at least one CPU requires
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* dynamic mitigation but others are either unaffected
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@ -50,7 +68,11 @@ static int32_t smccc_arch_features(u_register_t arg)
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/* Either the CPUs are unaffected or permanently mitigated */
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return SMCCC_ARCH_NOT_REQUIRED;
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#endif
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}
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#endif
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/* Fallthrough */
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default:
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return SMC_UNK;
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}
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