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tzc400: correct FAIL_CONTROL Privileged bit 

When bit 20 of TZC400 Fail control register [1] is set to 1, it means
Privileged access, the macros FAIL_CONTROL_PRIV_PRIV and
FAIL_CONTROL_PRIV_UNPRIV are then updated to reflect this.

 [1] https://developer.arm.com/documentation/ddi0504/c/programmers-model/register-descriptions/fail-control-register?lang=en

Change-Id: I01e522fded5cf66c9827293ddcf543c79f9e509e
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier 2020-11-06 15:32:25 +01:00 committed by Yann Gautier
parent 2c62b00e8c
commit 4f81ed8e1a
1 changed files with 2 additions and 2 deletions
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4
include/drivers/arm/tzc400.h
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@ -65,8 +65,8 @@
#define FAIL_CONTROL_NS_SECURE U(0)
#define FAIL_CONTROL_NS_NONSECURE U(1)
#define FAIL_CONTROL_PRIV_SHIFT 20
#define FAIL_CONTROL_PRIV_PRIV U(0)
#define FAIL_CONTROL_PRIV_UNPRIV U(1)
#define FAIL_CONTROL_PRIV_UNPRIV U(0)
#define FAIL_CONTROL_PRIV_PRIV U(1)
/*
* FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific.