tzc400: correct FAIL_CONTROL Privileged bit
When bit 20 of TZC400 Fail control register [1] is set to 1, it means Privileged access, the macros FAIL_CONTROL_PRIV_PRIV and FAIL_CONTROL_PRIV_UNPRIV are then updated to reflect this. [1] https://developer.arm.com/documentation/ddi0504/c/programmers-model/register-descriptions/fail-control-register?lang=en Change-Id: I01e522fded5cf66c9827293ddcf543c79f9e509e Signed-off-by: Yann Gautier <yann.gautier@st.com>
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@ -65,8 +65,8 @@
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#define FAIL_CONTROL_NS_SECURE U(0)
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#define FAIL_CONTROL_NS_SECURE U(0)
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#define FAIL_CONTROL_NS_NONSECURE U(1)
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#define FAIL_CONTROL_NS_NONSECURE U(1)
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#define FAIL_CONTROL_PRIV_SHIFT 20
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#define FAIL_CONTROL_PRIV_SHIFT 20
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#define FAIL_CONTROL_PRIV_PRIV U(0)
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#define FAIL_CONTROL_PRIV_UNPRIV U(0)
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#define FAIL_CONTROL_PRIV_UNPRIV U(1)
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#define FAIL_CONTROL_PRIV_PRIV U(1)
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/*
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/*
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* FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific.
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* FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific.
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