juno: Expose NIC-400 constants in the platform header file
It is easier to have all platform constants in the same place.
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@ -103,10 +103,14 @@ void bl1_early_platform_setup(void)
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}
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/*
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* Address of slave 'n' security setting in the NIC-400 address region
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* control
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* TODO: Ideally this macro should be moved in a "nic-400.h" header file but
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* it would be the only thing in there so it's not worth it at the moment.
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*/
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#define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4)
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#define SOC_NIC400_S5_BIT_UART1 (1u << 12)
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static void init_nic400(void)
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{
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/*
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@ -119,20 +123,30 @@ static void init_nic400(void)
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/*
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* Allow non-secure access to some SOC regions, excluding UART1, which
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* remains secure. Note: This is a NIC-400 device on the SOC
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* remains secure.
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* Note: This is the NIC-400 device on the SOC
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*/
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mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(0), ~0); // USB_EHCI
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mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(1), ~0); // TLX_MASTER
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mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(2), ~0); // USB_OHCI
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mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(3), ~0);
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mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(4), ~0); // PCIe
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mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(5), ~SOC_NIC400_S5_BIT_UART1);
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mmio_write_32(SOC_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_EHCI), ~0);
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mmio_write_32(SOC_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_TLX_MASTER), ~0);
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mmio_write_32(SOC_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_OHCI), ~0);
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mmio_write_32(SOC_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_PL354_SMC), ~0);
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mmio_write_32(SOC_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_APB4_BRIDGE), ~0);
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mmio_write_32(SOC_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_BOOTSEC_BRIDGE),
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~SOC_NIC400_BOOTSEC_BRIDGE_UART1);
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/*
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* Allow non-secure access to some CSS regions.
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* Note: This is a NIC-400 device on the CSS
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* Note: This is the NIC-400 device on the CSS
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*/
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mmio_write_32(CSS_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(8), ~0);
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mmio_write_32(CSS_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE),
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~0);
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}
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@ -117,7 +117,6 @@
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/* Following covers Columbus Peripherals excluding NSROM and NSRAM */
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#define DEVICE0_BASE 0x20000000
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#define DEVICE0_SIZE 0x0e000000
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#define CSS_NIC400_BASE 0x2a000000
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#define TZC400_BASE 0x2a4a0000
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#define MHU_BASE 0x2b1f0000
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@ -127,7 +126,6 @@
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/* Following covers Juno Peripherals and PCIe expansion area */
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#define DEVICE1_BASE 0x40000000
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#define DEVICE1_SIZE 0x40000000
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#define SOC_NIC400_BASE 0x7fd00000
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#define PCIE_CONTROL_BASE 0x7ff20000
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#define DRAM_BASE 0x80000000
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@ -239,6 +237,36 @@
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#define PL011_UART3_BASE 0x1c0c0000
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#define PL011_BASE PL011_UART0_BASE
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/*******************************************************************************
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* NIC-400 related constants
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******************************************************************************/
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/* CSS NIC-400 Global Programmers View (GPV) */
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#define CSS_NIC400_BASE 0x2a000000
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/* The slave_bootsecure controls access to GPU, DMC and CS. */
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#define CSS_NIC400_SLAVE_BOOTSECURE 8
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/* SoC NIC-400 Global Programmers View (GPV) */
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#define SOC_NIC400_BASE 0x7fd00000
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#define SOC_NIC400_USB_EHCI 0
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#define SOC_NIC400_TLX_MASTER 1
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#define SOC_NIC400_USB_OHCI 2
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#define SOC_NIC400_PL354_SMC 3
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/*
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* The apb4_bridge controls access to:
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* - the PCIe configuration registers
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* - the MMU units for USB, HDLCD and DMA
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*/
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#define SOC_NIC400_APB4_BRIDGE 4
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/*
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* The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
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*/
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#define SOC_NIC400_BOOTSEC_BRIDGE 5
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#define SOC_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12)
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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