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Tegra186: register FIQ interrupt sources 

This patch registers all the FIQ interrupt sources during platform
setup. Currently we support AON and TOP watchdog timer interrupts.

Change-Id: Ibccd866f00d6b08b574f765538525f95b49c5549
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2015-12-28 18:12:59 -08:00
parent ac55f309f0
commit 50cd8646c5
3 changed files with 49 additions and 2 deletions
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10
plat/nvidia/tegra/include/t186/tegra_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -65,6 +65,14 @@
ACTLR_EL3_CPUECTLR_BIT | \
ACTLR_EL3_CPUACTLR_BIT)
/*******************************************************************************
* Secure IRQ definitions
******************************************************************************/
#define TEGRA186_TOP_WDT_IRQ 49
#define TEGRA186_AON_WDT_IRQ 50
#define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */
/*******************************************************************************
* Tegra Miscellanous register constants
******************************************************************************/

40
plat/nvidia/tegra/soc/t186/plat_setup.c
View File

@ -28,8 +28,18 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <context.h>
#include <context_mgmt.h>
#include <debug.h>
#include <denver.h>
#include <interrupt_mgmt.h>
#include <platform.h>
#include <tegra_def.h>
#include <tegra_private.h>
#include <xlat_tables.h>
/*******************************************************************************
@ -120,3 +130,33 @@ uint32_t plat_get_console_from_id(int id)
return tegra186_uart_addresses[id];
}
/* Secure IRQs for Tegra186 */
static const irq_sec_cfg_t tegra186_sec_irqs[] = {
{
TEGRA186_TOP_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
{
TEGRA186_AON_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
};
/*******************************************************************************
* Initialize the GIC and SGIs
******************************************************************************/
void plat_gic_setup(void)
{
tegra_gic_setup(tegra186_sec_irqs,
sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0]));
/*
* Initialize the FIQ handler only if the platform supports any
* FIQ interrupt sources.
*/
if (sizeof(tegra186_sec_irqs) > 0)
tegra_fiq_handler_setup();
}

1
plat/nvidia/tegra/soc/t186/plat_sip_calls.c
View File

@ -134,7 +134,6 @@ int plat_sip_handler(uint32_t smc_fid,
return 0;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;
}