Tegra186: register FIQ interrupt sources
This patch registers all the FIQ interrupt sources during platform setup. Currently we support AON and TOP watchdog timer interrupts. Change-Id: Ibccd866f00d6b08b574f765538525f95b49c5549 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* modification, are permitted provided that the following conditions are met:
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@ -65,6 +65,14 @@
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUACTLR_BIT)
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ACTLR_EL3_CPUACTLR_BIT)
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/*******************************************************************************
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* Secure IRQ definitions
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******************************************************************************/
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#define TEGRA186_TOP_WDT_IRQ 49
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#define TEGRA186_AON_WDT_IRQ 50
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#define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */
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/*******************************************************************************
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/*******************************************************************************
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* Tegra Miscellanous register constants
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* Tegra Miscellanous register constants
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******************************************************************************/
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******************************************************************************/
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@ -28,8 +28,18 @@
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* POSSIBILITY OF SUCH DAMAGE.
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <console.h>
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#include <console.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <denver.h>
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#include <interrupt_mgmt.h>
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#include <platform.h>
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#include <tegra_def.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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#include <xlat_tables.h>
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#include <xlat_tables.h>
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/*******************************************************************************
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/*******************************************************************************
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@ -120,3 +130,33 @@ uint32_t plat_get_console_from_id(int id)
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return tegra186_uart_addresses[id];
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return tegra186_uart_addresses[id];
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}
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}
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/* Secure IRQs for Tegra186 */
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static const irq_sec_cfg_t tegra186_sec_irqs[] = {
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{
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TEGRA186_TOP_WDT_IRQ,
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TEGRA186_SEC_IRQ_TARGET_MASK,
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INTR_TYPE_EL3,
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},
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{
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TEGRA186_AON_WDT_IRQ,
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TEGRA186_SEC_IRQ_TARGET_MASK,
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INTR_TYPE_EL3,
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},
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};
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/*******************************************************************************
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* Initialize the GIC and SGIs
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******************************************************************************/
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void plat_gic_setup(void)
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{
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tegra_gic_setup(tegra186_sec_irqs,
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sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0]));
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/*
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* Initialize the FIQ handler only if the platform supports any
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* FIQ interrupt sources.
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*/
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if (sizeof(tegra186_sec_irqs) > 0)
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tegra_fiq_handler_setup();
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}
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@ -134,7 +134,6 @@ int plat_sip_handler(uint32_t smc_fid,
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return 0;
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return 0;
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default:
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default:
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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break;
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break;
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}
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}
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