From 1329f9647ca392450f25108446acba6421175084 Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Tue, 23 Apr 2019 10:25:39 +0100 Subject: [PATCH 1/4] plat: imx8mm: Add imx8mm_private.h to the build Allows for exporting of FIP related methods cleanly in a private header. Signed-off-by: Bryan O'Donoghue Signed-off-by: Ying-Chun Liu (PaulLiu) Change-Id: I8523f1370312ed22ff7ca710cd916be52f725e3c --- plat/imx/imx8m/imx8mm/include/imx8mm_private.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 plat/imx/imx8m/imx8mm/include/imx8mm_private.h diff --git a/plat/imx/imx8m/imx8mm/include/imx8mm_private.h b/plat/imx/imx8m/imx8mm/include/imx8mm_private.h new file mode 100644 index 000000000..52d13f031 --- /dev/null +++ b/plat/imx/imx8m/imx8mm/include/imx8mm_private.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IMX8MM_PRIVATE_H +#define IMX8MM_PRIVATE_H + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void plat_imx8mm_io_setup(void); + +#endif /* IMX8MM_PRIVATE_H */ From ee4d094acf49905f65bab916411a338e81fe6279 Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Wed, 17 Apr 2019 16:09:26 +0100 Subject: [PATCH 2/4] plat: imx8mm: Add image io-storage logic for TBBR FIP booting Signed-off-by: Bryan O'Donoghue Signed-off-by: Ying-Chun Liu (PaulLiu) Change-Id: I9833a54d0938d70886ac88b1922b17edf1dee8e0 --- plat/imx/imx8m/imx8mm/imx8mm_io_storage.c | 300 ++++++++++++++++++++++ 1 file changed, 300 insertions(+) create mode 100644 plat/imx/imx8m/imx8mm/imx8mm_io_storage.c diff --git a/plat/imx/imx8m/imx8mm/imx8mm_io_storage.c b/plat/imx/imx8m/imx8mm/imx8mm_io_storage.c new file mode 100644 index 000000000..ff6687e13 --- /dev/null +++ b/plat/imx/imx8m/imx8mm/imx8mm_io_storage.c @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static const io_dev_connector_t *fip_dev_con; +static uintptr_t fip_dev_handle; + +#ifndef IMX8MM_FIP_MMAP +static const io_dev_connector_t *mmc_dev_con; +static uintptr_t mmc_dev_handle; + +static const io_block_spec_t mmc_fip_spec = { + .offset = IMX8MM_FIP_MMC_BASE, + .length = IMX8MM_FIP_SIZE +}; + +static const io_block_dev_spec_t mmc_dev_spec = { + /* It's used as temp buffer in block driver. */ + .buffer = { + .offset = IMX8MM_FIP_BASE, + /* do we need a new value? */ + .length = IMX8MM_FIP_SIZE + }, + .ops = { + .read = mmc_read_blocks, + .write = mmc_write_blocks, + }, + .block_size = MMC_BLOCK_SIZE, +}; + +static int open_mmc(const uintptr_t spec); + +#else +static const io_dev_connector_t *memmap_dev_con; +static uintptr_t memmap_dev_handle; + +static const io_block_spec_t fip_block_spec = { + .offset = IMX8MM_FIP_BASE, + .length = IMX8MM_FIP_SIZE +}; +static int open_memmap(const uintptr_t spec); +#endif + +static int open_fip(const uintptr_t spec); + +static const io_uuid_spec_t bl31_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, +}; + +static const io_uuid_spec_t bl32_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32, +}; + +static const io_uuid_spec_t bl32_extra1_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, +}; + +static const io_uuid_spec_t bl32_extra2_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, +}; + +static const io_uuid_spec_t bl33_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, +}; + +#if TRUSTED_BOARD_BOOT +static const io_uuid_spec_t tb_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FW_CERT, +}; + +static const io_uuid_spec_t trusted_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_KEY_CERT, +}; + +static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = { + .uuid = UUID_SOC_FW_KEY_CERT, +}; + +static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, +}; + +static const io_uuid_spec_t tos_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t soc_fw_content_cert_uuid_spec = { + .uuid = UUID_SOC_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, +}; + +static const io_uuid_spec_t nt_fw_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, +}; +#endif /* TRUSTED_BOARD_BOOT */ + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int (*check)(const uintptr_t spec); +}; + +static const struct plat_io_policy policies[] = { +#ifndef IMX8MM_FIP_MMAP + [FIP_IMAGE_ID] = { + &mmc_dev_handle, + (uintptr_t)&mmc_fip_spec, + open_mmc + }, +#else + [FIP_IMAGE_ID] = { + &memmap_dev_handle, + (uintptr_t)&fip_block_spec, + open_memmap + }, +#endif + [BL31_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_uuid_spec, + open_fip + }, + [BL32_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_uuid_spec, + open_fip + }, + [BL32_EXTRA1_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra1_uuid_spec, + open_fip + }, + [BL32_EXTRA2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra2_uuid_spec, + open_fip + }, + [BL33_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_uuid_spec, + open_fip + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_BOOT_FW_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tb_fw_cert_uuid_spec, + open_fip + }, + [SOC_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&soc_fw_key_cert_uuid_spec, + open_fip + }, + [TRUSTED_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&trusted_key_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_key_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_key_cert_uuid_spec, + open_fip + }, + [SOC_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&soc_fw_content_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_cert_uuid_spec, + open_fip + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + +static int open_fip(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if a Firmware Image Package is available */ + result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); + if (result == 0) { + result = io_open(fip_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using FIP\n"); + io_close(local_image_handle); + } + } + return result; +} + +#ifndef IMX8MM_FIP_MMAP +static int open_mmc(const uintptr_t spec) +{ + int result; + uintptr_t local_handle; + + result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(mmc_dev_handle, spec, &local_handle); + if (result == 0) { + io_close(local_handle); + } + } + return result; +} +#else +static int open_memmap(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(memmap_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using Memmap\n"); + io_close(local_image_handle); + } + } + return result; +} +#endif + +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result; + const struct plat_io_policy *policy; + + assert(image_id < ARRAY_SIZE(policies)); + + policy = &policies[image_id]; + result = policy->check(policy->image_spec); + assert(result == 0); + + *image_spec = policy->image_spec; + *dev_handle = *policy->dev_handle; + + return result; +} + +void plat_imx8mm_io_setup(void) +{ + int result __unused; + +#ifndef IMX8MM_FIP_MMAP + result = register_io_dev_block(&mmc_dev_con); + assert(result == 0); + + result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec, + &mmc_dev_handle); + assert(result == 0); + +#else + result = register_io_dev_memmap(&memmap_dev_con); + assert(result == 0); + + result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, + &memmap_dev_handle); + assert(result == 0); +#endif + + result = register_io_dev_fip(&fip_dev_con); + assert(result == 0); + + result = io_dev_open(fip_dev_con, (uintptr_t)NULL, + &fip_dev_handle); + assert(result == 0); +} From 37ac9b7f11ee803fb128203a4edabcad99c0e466 Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Thu, 30 May 2019 13:58:53 +0100 Subject: [PATCH 3/4] plat: imx8mm: Add initial defintions to facilitate FIP layout Adds a number of definitions consistent with the established WaRP7 equivalents specifying number of io_handles and block devices. Signed-off-by: Bryan O'Donoghue Signed-off-by: Ying-Chun Liu (PaulLiu) Change-Id: If1d7ef1ad3ac3dfc860f949392c7534ce8d206e3 --- plat/imx/imx8m/imx8mm/include/platform_def.h | 24 +++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index 1041459c8..ec915ad68 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -1,9 +1,11 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include + #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 @@ -34,11 +36,27 @@ #define PLAT_SDEI_NORMAL_PRI 0x20 #define PLAT_SDEI_SGI_PRIVATE U(9) +#if defined(NEED_BL2) +#define BL2_BASE U(0x920000) +#define BL2_LIMIT U(0x940000) +#define BL31_BASE U(0x900000) +#define BL31_LIMIT U(0x920000) +#define IMX8MM_FIP_BASE U(0x40310000) +#define IMX8MM_FIP_SIZE U(0x000200000) +#define IMX8MM_FIP_LIMIT U(FIP_BASE + FIP_SIZE) + +/* Define FIP image location on eMMC */ +#define IMX8MM_FIP_MMC_BASE U(0x100000) + +#define PLAT_IMX8MM_BOOT_MMC_BASE U(0x30B50000) /* SD */ +#else #define BL31_BASE U(0x920000) #define BL31_LIMIT U(0x940000) +#endif /* non-secure uboot base */ #define PLAT_NS_IMAGE_OFFSET U(0x40200000) +#define PLAT_NS_IMAGE_SIZE U(0x00100000) /* GICv3 base address */ #define PLAT_GICD_BASE U(0x38800000) @@ -127,3 +145,7 @@ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ #define IMX_WDOG_B_RESET + +#define MAX_IO_HANDLES 3U +#define MAX_IO_DEVICES 2U +#define MAX_IO_BLOCK_DEVICES 1U From e364a8c367f6cc130d94cb792c7597dd16480a15 Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Wed, 17 Apr 2019 16:07:11 +0100 Subject: [PATCH 4/4] plat: imx8mm: Add image load logic for TBBR FIP booting Signed-off-by: Bryan O'Donoghue Signed-off-by: Ying-Chun Liu (PaulLiu) Change-Id: I0557ce6d0aa5ab321cac1ee25280b96762024396 --- plat/imx/imx8m/imx8mm/imx8mm_image_load.c | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 plat/imx/imx8m/imx8mm/imx8mm_image_load.c diff --git a/plat/imx/imx8m/imx8mm/imx8mm_image_load.c b/plat/imx/imx8m/imx8mm/imx8mm_image_load.c new file mode 100644 index 000000000..3a030699c --- /dev/null +++ b/plat/imx/imx8m/imx8mm/imx8mm_image_load.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include + +void plat_flush_next_bl_params(void) +{ + flush_bl_params_desc(); +} + +bl_load_info_t *plat_get_bl_image_load_info(void) +{ + return get_bl_load_info_from_mem_params_desc(); +} + +bl_params_t *plat_get_next_bl_params(void) +{ + return get_next_bl_params_from_mem_params_desc(); +}