feat(smmu): configure SMMU Root interface
This change performs a basic configuration of the SMMU root registers interface on an RME enabled system. This permits enabling GPC checks for transactions originated from a non-secure or secure device upstream to an SMMU. It re-uses the boot time GPT base address and configuration programmed on the PE. The root register file offset is platform dependent and has to be supplied on a model command line. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I4f889be6b7afc2afb4d1d147c5c1c3ea68f32e07
This commit is contained in:
Olivier Deprez
parent
19a9cc3a1b
commit
52a314af25
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -9,6 +9,7 @@
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#include <drivers/arm/smmu_v3.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <arch_features.h>
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/* SMMU poll number of retries */
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#define SMMU_POLL_TIMEOUT_US U(1000)
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@ -79,14 +80,74 @@ int __init smmuv3_init(uintptr_t smmu_base)
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if (smmuv3_security_init(smmu_base) != 0)
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return -1;
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/* Check if the SMMU supports secure state */
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if ((mmio_read_32(smmu_base + SMMU_S_IDR1) &
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SMMU_S_IDR1_SECURE_IMPL) == 0U)
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return 0;
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#if ENABLE_RME
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if (get_armv9_2_feat_rme_support() != 0U) {
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if ((mmio_read_32(smmu_base + SMMU_ROOT_IDR0) &
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SMMU_ROOT_IDR0_ROOT_IMPL) == 0U) {
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WARN("Skip SMMU GPC configuration.\n");
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} else {
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uint64_t gpccr_el3 = read_gpccr_el3();
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uint64_t gptbr_el3 = read_gptbr_el3();
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/* SMMU_ROOT_GPT_BASE_CFG[16] is RES0. */
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gpccr_el3 &= ~(1UL << 16);
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/*
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* TODO: SMMU_ROOT_GPT_BASE_CFG is 64b in the spec,
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* but SMMU model only accepts 32b access.
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*/
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mmio_write_32(smmu_base + SMMU_ROOT_GPT_BASE_CFG,
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gpccr_el3);
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/*
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* pa_gpt_table_base[51:12] maps to GPTBR_EL3[39:0]
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* whereas it maps to SMMU_ROOT_GPT_BASE[51:12]
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* hence needs a 12 bit left shit.
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*/
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mmio_write_64(smmu_base + SMMU_ROOT_GPT_BASE,
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gptbr_el3 << 12);
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/*
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* ACCESSEN=1: SMMU- and client-originated accesses are
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* not terminated by this mechanism.
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* GPCEN=1: All clients and SMMU-originated accesses,
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* except GPT-walks, are subject to GPC.
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*/
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mmio_setbits_32(smmu_base + SMMU_ROOT_CR0,
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SMMU_ROOT_CR0_GPCEN |
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SMMU_ROOT_CR0_ACCESSEN);
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/* Poll for ACCESSEN and GPCEN ack bits. */
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if (smmuv3_poll(smmu_base + SMMU_ROOT_CR0ACK,
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SMMU_ROOT_CR0_GPCEN |
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SMMU_ROOT_CR0_ACCESSEN,
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SMMU_ROOT_CR0_GPCEN |
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SMMU_ROOT_CR0_ACCESSEN) != 0) {
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WARN("Failed enabling SMMU GPC.\n");
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/*
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* Do not return in error, but fall back to
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* invalidating all entries through the secure
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* register file.
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*/
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}
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}
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}
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#endif /* ENABLE_RME */
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/*
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* Initiate invalidation of secure caches and TLBs if the SMMU
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* supports secure state. If not, it's implementation defined
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* as to how SMMU_S_INIT register is accessed.
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* Arm SMMU Arch RME supplement, section 3.4: all SMMU registers
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* specified to be accessible only in secure physical address space are
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* additionally accessible in root physical address space in an SMMU
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* with RME.
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* Section 3.3: as GPT information is permitted to be cached in a TLB,
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* the SMMU_S_INIT.INV_ALL mechanism also invalidates GPT information
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* cached in TLBs.
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*/
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mmio_write_32(smmu_base + SMMU_S_INIT, SMMU_S_INIT_INV_ALL);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -9,6 +9,7 @@
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#include <stdint.h>
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#include <lib/utils_def.h>
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#include <platform_def.h>
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/* SMMUv3 register offsets from device base */
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#define SMMU_GBPA U(0x0044)
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@ -16,6 +17,26 @@
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#define SMMU_S_INIT U(0x803c)
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#define SMMU_S_GBPA U(0x8044)
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/*
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* TODO: SMMU_ROOT_PAGE_OFFSET is platform specific.
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* Currently defined as a command line model parameter.
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*/
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#if ENABLE_RME
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#define SMMU_ROOT_PAGE_OFFSET (PLAT_ARM_SMMUV3_ROOT_REG_OFFSET)
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#define SMMU_ROOT_IDR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0000)
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#define SMMU_ROOT_IIDR U(SMMU_ROOT_PAGE_OFFSET + 0x0008)
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#define SMMU_ROOT_CR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0020)
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#define SMMU_ROOT_CR0ACK U(SMMU_ROOT_PAGE_OFFSET + 0x0024)
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#define SMMU_ROOT_GPT_BASE U(SMMU_ROOT_PAGE_OFFSET + 0x0028)
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#define SMMU_ROOT_GPT_BASE_CFG U(SMMU_ROOT_PAGE_OFFSET + 0x0030)
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#define SMMU_ROOT_GPF_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0038)
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#define SMMU_ROOT_GPT_CFG_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0040)
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#define SMMU_ROOT_TLBI U(SMMU_ROOT_PAGE_OFFSET + 0x0050)
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#define SMMU_ROOT_TLBI_CTRL U(SMMU_ROOT_PAGE_OFFSET + 0x0058)
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#endif /* ENABLE_RME */
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/* SMMU_GBPA register fields */
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#define SMMU_GBPA_UPDATE (1UL << 31)
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#define SMMU_GBPA_ABORT (1UL << 20)
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@ -30,6 +51,13 @@
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#define SMMU_S_GBPA_UPDATE (1UL << 31)
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#define SMMU_S_GBPA_ABORT (1UL << 20)
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/* SMMU_ROOT_IDR0 register fields */
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#define SMMU_ROOT_IDR0_ROOT_IMPL (1UL << 0)
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/* SMMU_ROOT_CR0 register fields */
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#define SMMU_ROOT_CR0_GPCEN (1UL << 1)
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#define SMMU_ROOT_CR0_ACCESSEN (1UL << 0)
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int smmuv3_init(uintptr_t smmu_base);
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int smmuv3_security_init(uintptr_t smmu_base);
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@ -261,6 +261,7 @@
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#define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ
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#define PLAT_FVP_SMMUV3_BASE UL(0x2b400000)
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#define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000)
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/* CCI related constants */
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#define PLAT_FVP_CCI400_BASE UL(0x2c090000)
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