Merge pull request #770 from yatharth-arm/yk/AArch32_fixes
AArch32: Miscellaneous fixes in the AArch32 code
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commit
535f185a5c
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@ -118,15 +118,15 @@ func console_core_putc
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1:
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/* Check if the transmit FIFO is full */
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ldr r2, [r1, #UARTFR]
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tst r2, #PL011_UARTFR_TXFF_BIT
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beq 1b
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tst r2, #PL011_UARTFR_TXFF
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bne 1b
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mov r2, #0xD
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str r2, [r1, #UARTDR]
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2:
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/* Check if the transmit FIFO is full */
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ldr r2, [r1, #UARTFR]
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tst r2, #PL011_UARTFR_TXFF_BIT
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beq 2b
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tst r2, #PL011_UARTFR_TXFF
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bne 2b
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str r0, [r1, #UARTDR]
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bx lr
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putc_error:
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@ -149,8 +149,8 @@ func console_core_getc
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1:
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/* Check if the receive FIFO is empty */
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ldr r1, [r0, #UARTFR]
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tst r1, #PL011_UARTFR_RXFE_BIT
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beq 1b
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tst r1, #PL011_UARTFR_RXFE
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bne 1b
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ldr r1, [r0, #UARTDR]
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mov r0, r1
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bx lr
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@ -109,7 +109,13 @@
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msr spsr_und, r9
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msr sp_und, r10
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msr lr_und, r11
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msr spsr, r12
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/*
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* Use the `_fsxc` suffix explicitly to instruct the assembler
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* to update all the 32 bits of SPSR. Else, by default, the
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* assembler assumes `_fc` suffix which only modifies
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* f->[31:24] and c->[7:0] bits of SPSR.
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*/
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msr spsr_fsxc, r12
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/* Restore the rest of the general purpose registers */
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ldm r0, {r0-r12}
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@ -31,26 +31,11 @@
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#include <arch.h>
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#include <asm_macros.S>
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.weak plat_my_core_pos
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.weak plat_reset_handler
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.weak plat_disable_acp
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.weak platform_mem_init
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.weak plat_panic_handler
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/* -----------------------------------------------------
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* int plat_my_core_pos(void);
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* With this function: CorePos = (ClusterId * 4) +
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* CoreId
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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ldcopr r0, MPIDR
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and r1, r0, #MPIDR_CPU_MASK
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and r0, r0, #MPIDR_CLUSTER_MASK
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add r0, r1, r0, LSR #6
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bx lr
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* Placeholder function which should be redefined by
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* each platform.
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