rcar_gen3: drivers: ddr-b: Synchronize tables

Synchronize the R-Car DDR-B driver, used on R-Car H3/M3W/M3N,
with Renesas ATF release 2.0.0 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c

@@ -4,24 +4,33 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#define BOARDNUM 16
+#define BOARDNUM 18
 #define BOARD_JUDGE_AUTO
 
+#ifdef BOARD_JUDGE_AUTO
 static uint32_t _board_judge(void);
 
 static uint32_t boardcnf_get_brd_type(void)
 {
 	return _board_judge();
 }
+#else
+static uint32_t boardcnf_get_brd_type(void)
+{
+	return (1);
+}
+#endif
+
+#define DDR_FAST_INIT
 
 struct _boardcnf_ch {
 	uint8_t ddr_density[CS_CNT];
-	uint32_t ca_swap;
+	uint64_t ca_swap;
 	uint16_t dqs_swap;
 	uint32_t dq_swap[SLICE_CNT];
 	uint8_t dm_swap[SLICE_CNT];
 	uint16_t wdqlvl_patt[16];
-	int8_t cacs_adj[10];
+	int8_t cacs_adj[16];
 	int8_t dm_adj_w[SLICE_CNT];
 	int8_t dq_adj_w[SLICE_CNT * 8];
 	int8_t dm_adj_r[SLICE_CNT];
@@ -876,7 +885,11 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0x0a0,
 	 {
 	  {
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
+	   {0x04, 0x04},
+#else
 	   {0x02, 0x02},
+#endif
 	   0x00342501,
 	   0x3201,
 	   {0x10672534, 0x43257106, 0x34527601, 0x71605243},
@@ -1227,7 +1240,89 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   }
 	  }
+	 },
+/* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */
+	{
+	 0x03,
+	 0x01,
+	 0x0320,
+	 0,
+	 0x0300,
+	 0x00a0,
+	 {
+	  {
+	   {0x04, 0x04},
+	    0x520314FFFF523041,
+	    0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	    WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x04, 0x04},
+	    0x314250FFFF312405,
+	    0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	    WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */
+	{
+	 0x01,
+	 0x01,
+	 0x0300,
+	 0,
+	 0x0300,
+	 0x00a0,
+	 {
+	  {
+	   {0x04, 0x04},
+	    0x520314FFFF523041,
+	    0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	    WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	  }
 	 }
+	}
 };
 
 void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
@@ -1258,6 +1353,7 @@ void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
 			break;
 		}
 	}
+	(void)brd;
 }
 
 void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
@@ -1284,6 +1380,7 @@ void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
 		*div = 1;
 		break;
 	}
+	(void)brd;
 }
 
 #define _def_REFPERIOD  1890
@@ -1393,10 +1490,10 @@ static uint32_t opencheck_SSI_WS6(void)
 	if (down == up) {
 		/* Same = Connect */
 		return 0;
+	} else {
+		/* Diff = Open */
+		return 1;
 	}
-
-	/* Diff = Open */
-	return 1;
 }
 
 #endif
@@ -1431,6 +1528,7 @@ static uint32_t _board_judge(void)
 	usb2_ovc_open = opencheck_SSI_WS6();
 
 	/* RENESAS Eva-borad */
+	brd = 99;
 	if (Prr_Product == PRR_PRODUCT_V3H) {
 		/* RENESAS Condor board */
 		brd = 12;
@@ -1441,10 +1539,12 @@ static uint32_t _board_judge(void)
 		} else if (Prr_Product == PRR_PRODUCT_M3) {
 			/* RENESAS Kriek board with M3-W */
 			brd = 1;
-		} else if (Prr_Cut <= PRR_PRODUCT_11) {
+		} else if ((Prr_Product == PRR_PRODUCT_H3)
+			   && (Prr_Cut<=PRR_PRODUCT_11)) {
 			/* RENESAS Kriek board with PM3 */
 			brd = 13;
-		} else {
+		} else if ((Prr_Product == PRR_PRODUCT_H3)
+			   && (Prr_Cut > PRR_PRODUCT_20)) {
 			/* RENESAS Kriek board with H3N */
 			brd = 15;
 		}
@@ -1467,12 +1567,13 @@ static uint32_t _board_judge(void)
 		} else if (Prr_Product == PRR_PRODUCT_M3N) {
 			/* RENESAS SALVATOR-X (M3-N/SIP) */
 			brd = 11;
-		} else {
+		} else if (Prr_Product == PRR_PRODUCT_M3) {
 			/* RENESAS SALVATOR-X (M3-W/SIP) */
 			brd = 0;
 		}
 	}
 #endif
+
 	return brd;
 }
 #endif

drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#define RCAR_DDR_VERSION        "rev.0.33"
+#define RCAR_DDR_VERSION        "rev.0.34"
 #define DRAM_CH_CNT		(0x04)
 #define SLICE_CNT		(0x04)
 #define CS_CNT			(0x02)

drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h

@@ -267,7 +267,7 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
 /*0bb9*/ 0x00000000,
 /*0bba*/ 0x00000000,
 /*0bbb*/ 0x00000000,
-/*0bbc*/ 0x00000065,
+/*0bbc*/ 0x00000265,
 /*0bbd*/ 0x00000000,
 /*0bbe*/ 0x00040401,
 /*0bbf*/ 0x00000000,

drivers/staging/renesas/rcar/ddr/dram_sub_func.c

@@ -19,10 +19,11 @@
 #define PRR_PRODUCT_V3H			(0x00005600U)	/* R-Car V3H */
 
 #if RCAR_SYSTEM_SUSPEND
-#include "iic_dvfs.h"
+/* Local defines */
-
 #define DRAM_BACKUP_GPIO_USE		(0)
+#include "iic_dvfs.h"
 #if PMIC_ROHM_BD9571
+#define	PMIC_SLAVE_ADDR			(0x30U)
 #define	PMIC_BKUP_MODE_CNT		(0x20U)
 #define	PMIC_QLLM_CNT			(0x27U)
 #define	BIT_BKUP_CTRL_OUT		((uint8_t)(1U << 4U))
@@ -52,40 +53,53 @@
 void rcar_dram_get_boot_status(uint32_t * status)
 {
 #if RCAR_SYSTEM_SUSPEND
-	uint32_t shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
+
-	uint32_t gpio = GPIO_INDT1;
+	uint32_t reg_data;
-	uint32_t reg, product;
+	uint32_t product;
+	uint32_t shift;
+	uint32_t gpio;
 
 	product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
-
 	if (product == PRR_PRODUCT_V3H) {
 		shift = GPIO_BKUP_TRG_SHIFT_CONDOR;
 		gpio = GPIO_INDT3;
 	} else if (product == PRR_PRODUCT_E3) {
 		shift = GPIO_BKUP_TRG_SHIFT_EBISU;
 		gpio = GPIO_INDT6;
+	} else {
+		shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
+		gpio = GPIO_INDT1;
 	}
 
-	reg = mmio_read_32(gpio) & (1U << shift);
+	reg_data = mmio_read_32(gpio);
-	*status = reg ? DRAM_BOOT_STATUS_WARM : DRAM_BOOT_STATUS_COLD;
+	if (0U != (reg_data & ((uint32_t)1U << shift))) {
-#else
+		*status = DRAM_BOOT_STATUS_WARM;
+	} else {
+		*status = DRAM_BOOT_STATUS_COLD;
+	}
+#else	/* RCAR_SYSTEM_SUSPEND */
 	*status = DRAM_BOOT_STATUS_COLD;
-#endif
+#endif	/* RCAR_SYSTEM_SUSPEND */
 }
 
 int32_t rcar_dram_update_boot_status(uint32_t status)
 {
 	int32_t ret = 0;
 #if RCAR_SYSTEM_SUSPEND
+	uint32_t reg_data;
 #if PMIC_ROHM_BD9571
 #if DRAM_BACKUP_GPIO_USE == 0
-	uint8_t mode = 0U;
+	uint8_t bkup_mode_cnt = 0U;
 #else
 	uint32_t reqb, outd;
 #endif
-	uint8_t qllm = 0;
+	uint8_t qllm_cnt = 0U;
+	int32_t i2c_dvfs_ret = -1;
 #endif
-	uint32_t i, product, trg, gpio;
+	uint32_t loop_count;
+	uint32_t product;
+	uint32_t trg;
+	uint32_t gpio;
 
 	product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
 	if (product == PRR_PRODUCT_V3H) {
@@ -111,50 +125,58 @@ int32_t rcar_dram_update_boot_status(uint32_t status)
 		gpio = GPIO_INDT1;
 	}
 
-	if (status != DRAM_BOOT_STATUS_WARM)
+	if (status == DRAM_BOOT_STATUS_WARM) {
-		goto cold;
-
 #if DRAM_BACKUP_GPIO_USE==1
 	mmio_setbits_32(outd, 1U << reqb);
 #else
-
 #if PMIC_ROHM_BD9571
-	if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode)) {
+		/* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */
-		ERROR("BKUP mode cnt READ ERROR.\n");
+		i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR,
-		return DRAM_UPDATE_STATUS_ERR;
+				PMIC_BKUP_MODE_CNT, &bkup_mode_cnt);
+		if (0 != i2c_dvfs_ret) {
+			ERROR("BKUP mode cnt READ ERROR.\n");
+			ret = DRAM_UPDATE_STATUS_ERR;
+		} else {
+			bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT;
+			i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
+					PMIC_BKUP_MODE_CNT, bkup_mode_cnt);
+			if (0 != i2c_dvfs_ret) {
+				ERROR("BKUP mode cnt WRITE ERROR. "
+					"value = %d\n", bkup_mode_cnt);
+				ret = DRAM_UPDATE_STATUS_ERR;
+			}
+		}
+#endif /* PMIC_ROHM_BD9571 */
+#endif /* DRAM_BACKUP_GPIO_USE==1 */
+		/* Wait BKUP_TRG=Low */
+		loop_count = DRAM_BKUP_TRG_LOOP_CNT;
+		while (0U < loop_count) {
+			reg_data = mmio_read_32(gpio);
+			if ((reg_data &
+				((uint32_t)1U << trg)) == 0U) {
+				break;
+			}
+			loop_count--;
+		}
+		if (0U == loop_count) {
+			ERROR(	"\nWarm booting...\n" \
+				" The potential of BKUP_TRG did not switch " \
+				"to Low.\n If you expect the operation of " \
+				"cold boot,\n check the board configuration" \
+				" (ex, Dip-SW) and/or the H/W failure.\n");
+			ret = DRAM_UPDATE_STATUS_ERR;
+		}
 	}
-
-	mode &= ~BIT_BKUP_CTRL_OUT;
-	if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode)) {
-		ERROR("BKUP mode cnt WRITE ERROR. value = %d\n", mode);
-		return DRAM_UPDATE_STATUS_ERR;
-	}
-#endif
-#endif
-	for (i = 0; i < DRAM_BKUP_TRG_LOOP_CNT; i++) {
-		if (mmio_read_32(gpio) & (1U << trg))
-			continue;
-
-		goto cold;
-	}
-
-	ERROR("\nWarm booting Error...\n"
-	      " The potential of BKUP_TRG did not switch "
-	      "to Low.\n If you expect the operation of "
-	      "cold boot,\n check the board configuration"
-	      " (ex, Dip-SW) and/or the H/W failure.\n");
-
-	return DRAM_UPDATE_STATUS_ERR;
-
-cold:
 #if PMIC_ROHM_BD9571
-	if (ret)
+	if(0 == ret) {
-		return ret;
+		qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
-
+		i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
-	qllm = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
+				PMIC_QLLM_CNT, qllm_cnt);
-	if (rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, qllm)) {
+		if (0 != i2c_dvfs_ret) {
-		ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm);
+			ERROR("QLLM cnt WRITE ERROR. "
-		ret = DRAM_UPDATE_STATUS_ERR;
+				"value = %d\n", qllm_cnt);
+			ret = DRAM_UPDATE_STATUS_ERR;
+		}
 	}
 #endif
 #endif