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feat(plat/rcar3): modify LifeC register setting for R-Car D3 

Modified SECGRP0COND6 and SECGRP1COND6 setting for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I3f173ac44c11743965c013ef238748b0dc8cabab
This commit is contained in:
Toshiyuki Ogasahara 2021-07-12 19:24:29 +09:00 committed by Marek Vasut
parent 053c134683
commit 5460f82806
1 changed files with 6 additions and 6 deletions
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12
plat/renesas/common/bl2_secure_setting.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -49,10 +49,10 @@ static const struct {
/*
* Bit13: SCEG PKA (secure APB) slave ports
* 0: registers accessed from secure resource only
* 1: Reserved[R-Car E3]
* 1: Reserved[R-Car E3/D3]
* Bit12: SCEG PKA (public APB) slave ports
* 0: registers accessed from secure resource only
* 1: Reserved[R-Car E3]
* 1: Reserved[R-Car E3/D3]
* Bit10: SCEG Secure Core slave ports
* 0: registers accessed from secure resource only
*/
@ -152,14 +152,14 @@ static const struct {
* Security group 1 attribute setting for slave ports 6
* Bit13: SCEG PKA (secure APB) slave ports
* SecurityGroup3
* Reserved[R-Car E3]
* Reserved[R-Car E3/D3]
* Bit12: SCEG PKA (public APB) slave ports
* SecurityGroup3
* Reserved[R-Car E3]
* Reserved[R-Car E3/D3]
* Bit10: SCEG Secure Core slave ports
* SecurityGroup3
*/
#if RCAR_LSI == RCAR_E3
#if RCAR_LSI == RCAR_E3 || RCAR_LSI == RCAR_D3
{ SEC_GRP0COND6, 0x00000400U },
{ SEC_GRP1COND6, 0x00000400U },
#else /* RCAR_LSI == RCAR_E3 */