Tegra194: support for NVG interface v6.6
This patch updates the NVG interface header file to v6.6. Change-Id: I2f5df274bf820ba1c5df47d8dcbf7f5f056ff45f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar
parent
844e6cc5e7
commit
54990e377c
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@ -20,61 +20,65 @@
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*/
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enum {
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TEGRA_NVG_VERSION_MAJOR = 6,
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TEGRA_NVG_VERSION_MINOR = 4
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TEGRA_NVG_VERSION_MINOR = 6
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};
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typedef enum {
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TEGRA_NVG_CHANNEL_VERSION = 0,
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TEGRA_NVG_CHANNEL_POWER_PERF = 1,
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TEGRA_NVG_CHANNEL_POWER_MODES = 2,
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TEGRA_NVG_CHANNEL_WAKE_TIME = 3,
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TEGRA_NVG_CHANNEL_CSTATE_INFO = 4,
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TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5,
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TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6,
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TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8,
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TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10,
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TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11,
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TEGRA_NVG_CHANNEL_SHUTDOWN = 42,
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TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43,
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TEGRA_NVG_CHANNEL_ONLINE_CORE = 44,
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TEGRA_NVG_CHANNEL_CC3_CTRL = 45,
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TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49,
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TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50,
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TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53,
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TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54,
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TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55,
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TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56,
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TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57,
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TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58,
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TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59,
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TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60,
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TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61,
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TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62,
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TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76,
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TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77,
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TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78,
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TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79,
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TEGRA_NVG_CHANNEL_VERSION = 0,
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TEGRA_NVG_CHANNEL_POWER_PERF = 1,
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TEGRA_NVG_CHANNEL_POWER_MODES = 2,
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TEGRA_NVG_CHANNEL_WAKE_TIME = 3,
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TEGRA_NVG_CHANNEL_CSTATE_INFO = 4,
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TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5,
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TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6,
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TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8,
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TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10,
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TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11,
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TEGRA_NVG_CHANNEL_NUM_CORES = 20,
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TEGRA_NVG_CHANNEL_UNIQUE_LOGICAL_ID = 21,
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TEGRA_NVG_CHANNEL_LOGICAL_TO_PHYSICAL_MAPPING = 22,
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TEGRA_NVG_CHANNEL_LOGICAL_TO_MPIDR = 23,
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TEGRA_NVG_CHANNEL_SHUTDOWN = 42,
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TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43,
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TEGRA_NVG_CHANNEL_ONLINE_CORE = 44,
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TEGRA_NVG_CHANNEL_CC3_CTRL = 45,
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TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49,
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TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50,
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TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53,
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TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54,
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TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55,
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TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56,
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TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57,
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TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58,
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TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59,
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TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60,
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TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61,
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TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62,
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TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75,
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TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76,
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TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77,
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TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78,
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TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79,
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TEGRA_NVG_CHANNEL_LAST_INDEX
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} tegra_nvg_channel_id_t;
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typedef enum {
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NVG_STAT_QUERY_SC7_ENTRIES = 1,
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NVG_STAT_QUERY_CC6_ENTRIES = 6,
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NVG_STAT_QUERY_CG7_ENTRIES = 7,
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NVG_STAT_QUERY_SC7_ENTRIES = 1,
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NVG_STAT_QUERY_CC6_ENTRIES = 6,
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NVG_STAT_QUERY_CG7_ENTRIES = 7,
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NVG_STAT_QUERY_C6_ENTRIES = 10,
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NVG_STAT_QUERY_C7_ENTRIES = 14,
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NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32,
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@ -112,8 +116,14 @@ typedef enum {
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TEGRA_NVG_CORE_WARMRSTREQ = 8
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} tegra_nvg_core_sleep_state_t;
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typedef enum {
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TEGRA_NVG_SHUTDOWN = 0U,
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TEGRA_NVG_REBOOT = 1U
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} tegra_nvg_shutdown_reboot_state_t;
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typedef enum {
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TEGRA_NVG_CLUSTER_CC0 = 0,
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TEGRA_NVG_CLUSTER_AUTO_CC1 = 1,
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TEGRA_NVG_CLUSTER_CC6 = 6
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} tegra_nvg_cluster_sleep_state_t;
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@ -128,11 +138,6 @@ typedef enum {
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TEGRA_NVG_SYSTEM_SC8 = 8
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} tegra_nvg_system_sleep_state_t;
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typedef enum {
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TEGRA_NVG_SHUTDOWN = 0U,
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TEGRA_NVG_REBOOT = 1U,
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} tegra_nvg_shutdown_reboot_state_t;
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// ---------------------------------------------------------------------------
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// NVG Data subformats
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// ---------------------------------------------------------------------------
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@ -206,18 +211,31 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_cstate_info_channel_t {
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uint32_t cluster_state : 3;
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uint32_t reserved_6_3 : 4;
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uint32_t update_cluster : 1;
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uint32_t cg_cstate : 3;
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uint32_t reserved_14_11 : 4;
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uint32_t update_cg : 1;
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uint32_t system_cstate : 4;
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uint32_t reserved_22_20 : 3;
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uint32_t update_system : 1;
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uint32_t reserved_30_24 : 7;
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uint32_t update_wake_mask : 1;
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uint32_t wake_mask : 32;
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uint32_t cluster_state : 3;
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uint32_t reserved_6_3 : 4;
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uint32_t update_cluster : 1;
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uint32_t cg_cstate : 3;
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uint32_t reserved_14_11 : 4;
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uint32_t update_cg : 1;
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uint32_t system_cstate : 4;
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uint32_t reserved_22_20 : 3;
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uint32_t update_system : 1;
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uint32_t reserved_30_24 : 7;
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uint32_t update_wake_mask : 1;
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union {
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uint32_t flat : 32;
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struct {
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uint32_t vfiq : 1;
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uint32_t virq : 1;
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uint32_t fiq : 1;
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uint32_t irq : 1;
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uint32_t serror : 1;
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uint32_t reserved_10_5 : 6;
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uint32_t fiqout : 1;
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uint32_t irqout : 1;
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uint32_t reserved_31_13 : 19;
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} carmel;
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} wake_mask;
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} bits;
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} nvg_cstate_info_channel_t;
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@ -239,6 +257,52 @@ typedef union {
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} bits;
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} nvg_cstate_stat_query_channel_t;
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typedef union {
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uint64_t flat;
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struct nvg_num_cores_channel_t {
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uint32_t num_cores : 4;
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uint32_t reserved_31_4 : 28;
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uint32_t reserved_63_32 : 32;
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} bits;
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} nvg_num_cores_channel_t;
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typedef union {
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uint64_t flat;
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struct nvg_unique_logical_id_channel_t {
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uint32_t unique_core_id : 3;
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uint32_t reserved_31_3 : 29;
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uint32_t reserved_63_32 : 32;
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} bits;
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} nvg_unique_logical_id_channel_t;
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typedef union {
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uint64_t flat;
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struct nvg_logical_to_physical_mappings_channel_t {
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uint32_t lcore0_pcore_id : 4;
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uint32_t lcore1_pcore_id : 4;
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uint32_t lcore2_pcore_id : 4;
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uint32_t lcore3_pcore_id : 4;
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uint32_t lcore4_pcore_id : 4;
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uint32_t lcore5_pcore_id : 4;
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uint32_t lcore6_pcore_id : 4;
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uint32_t lcore7_pcore_id : 4;
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uint32_t reserved_63_32 : 32;
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} bits;
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} nvg_logical_to_physical_mappings_channel_t;
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typedef union {
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uint64_t flat;
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struct nvg_logical_to_mpidr_channel_write_t {
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uint32_t lcore_id : 3;
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uint32_t reserved_31_3 : 29;
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uint32_t reserved_63_32 : 32;
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} write;
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struct nvg_logical_to_mpidr_channel_read_t {
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uint32_t mpidr : 32;
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uint32_t reserved_63_32 : 32;
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} read;
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} nvg_logical_to_mpidr_channel_t;
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typedef union {
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uint64_t flat;
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struct nvg_is_sc7_allowed_channel_t {
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@ -260,50 +324,50 @@ typedef union {
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typedef union {
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uint64_t flat;
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struct nvg_cc3_control_channel_t {
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uint32_t freq_req : 8;
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uint32_t reserved_30_8 : 23;
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uint32_t freq_req : 9;
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uint32_t reserved_30_9 : 22;
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uint32_t enable : 1;
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uint32_t reserved_63_32 : 32;
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} bits;
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} nvg_cc3_control_channel_t;
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typedef enum {
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TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35,
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TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX
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} tegra_nvg_channel_update_gsc_gsc_enum_t;
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@ -335,4 +399,26 @@ typedef union {
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} bits;
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} nvg_shutdown_t;
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typedef union {
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uint64_t flat;
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struct nvg_debug_config_channel_t {
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uint32_t enter_debug_state_on_mca : 1;
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uint32_t reserved_31_1 : 31;
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uint32_t reserved_63_32 : 32;
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} bits;
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} nvg_debug_config_t;
|
||||
|
||||
typedef union {
|
||||
uint64_t flat;
|
||||
struct nvg_hsm_error_ctrl_channel_t {
|
||||
uint32_t uncorr : 1;
|
||||
uint32_t corr : 1;
|
||||
uint32_t reserved_31_2 : 30;
|
||||
uint32_t reserved_63_32 : 32;
|
||||
} bits;
|
||||
} nvg_hsm_error_ctrl_channel_t;
|
||||
|
||||
extern nvg_debug_config_t nvg_debug_config;
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue