From 568ac1f730a3a7445b81c6b396d354e320ef8e6a Mon Sep 17 00:00:00 2001 From: David Cunado Date: Thu, 1 Jun 2017 12:48:39 +0100 Subject: [PATCH] Resolve build errors flagged by GCC 6.2 With GCC 6.2 compiler, more C undefined behaviour is being flagged as warnings, which result in build errors in ARM TF build. This patch addresses issue caused by enums with values that exceed maximum value for an int. For these cases the enum is converted to a set of defines. Change-Id: I5114164be10d86d5beef3ea1ed9be5863855144d Signed-off-by: David Cunado --- plat/mediatek/mt6795/include/mcucfg.h | 12 +++++------- plat/mediatek/mt8173/include/mcucfg.h | 12 +++++------- 2 files changed, 10 insertions(+), 14 deletions(-) diff --git a/plat/mediatek/mt6795/include/mcucfg.h b/plat/mediatek/mt6795/include/mcucfg.h index c81de3320..eff8d3440 100644 --- a/plat/mediatek/mt6795/include/mcucfg.h +++ b/plat/mediatek/mt6795/include/mcucfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -104,12 +104,10 @@ struct mt6795_mcucfg_regs { static struct mt6795_mcucfg_regs *const mt6795_mcucfg = (void *)MCUCFG_BASE; /* cpu boot mode */ -enum { - MP0_CPUCFG_64BIT_SHIFT = 12, - MP1_CPUCFG_64BIT_SHIFT = 28, - MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT, - MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT -}; +#define MP0_CPUCFG_64BIT_SHIFT 12 +#define MP1_CPUCFG_64BIT_SHIFT 28 +#define MP0_CPUCFG_64BIT (U(0xf) << MP0_CPUCFG_64BIT_SHIFT) +#define MP1_CPUCFG_64BIT (U(0xf) << MP1_CPUCFG_64BIT_SHIFT) /* scu related */ enum { diff --git a/plat/mediatek/mt8173/include/mcucfg.h b/plat/mediatek/mt8173/include/mcucfg.h index 23d833293..355c276e5 100644 --- a/plat/mediatek/mt8173/include/mcucfg.h +++ b/plat/mediatek/mt8173/include/mcucfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -103,12 +103,10 @@ struct mt8173_mcucfg_regs { static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE; /* cpu boot mode */ -enum { - MP0_CPUCFG_64BIT_SHIFT = 12, - MP1_CPUCFG_64BIT_SHIFT = 28, - MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT, - MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT -}; +#define MP0_CPUCFG_64BIT_SHIFT 12 +#define MP1_CPUCFG_64BIT_SHIFT 28 +#define MP0_CPUCFG_64BIT (U(0xf) << MP0_CPUCFG_64BIT_SHIFT) +#define MP1_CPUCFG_64BIT (U(0xf) << MP1_CPUCFG_64BIT_SHIFT) /* scu related */ enum {