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Merge changes from topic "k3-cleanups" into integration 

* changes:
  ti: k3: common: Align elements of map region table
  ti: k3: common: Enable SEPARATE_CODE_AND_RODATA by default
  ti: k3: common: Remove shared RAM space
  ti: k3: common: Drop _ADDRESS from K3_USART_BASE to match other defines
This commit is contained in:
Antonio Niño Díaz 2019-04-24 10:03:59 +00:00 committed by TrustedFirmware Code Review
parent d87af648a2 883eab2bd3
commit 568bfb7b3f
4 changed files with 17 additions and 24 deletions
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18
plat/ti/k3/common/k3_bl31_setup.c
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@ -21,10 +21,9 @@
/* Table of regions to map using the MMU */
const mmap_region_t plat_k3_mmap[] = {
MAP_REGION_FLAT(SHARED_RAM_BASE, SHARED_RAM_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(K3_USART_BASE_ADDRESS, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
{ /* sentinel */ }
@ -100,13 +99,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
void bl31_plat_arch_setup(void)
{
const mmap_region_t bl_regions[] = {
MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE),
MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_END,
MT_RO_DATA | MT_SECURE),
{0}
MAP_REGION_FLAT(BL31_START, BL31_END - BL31_START, MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_RO | MT_SECURE),
MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_END, MT_RO_DATA | MT_RO | MT_SECURE),
{ /* sentinel */ }
};
setup_page_tables(bl_regions, plat_k3_mmap);

2
plat/ti/k3/common/k3_console.c
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@ -16,6 +16,6 @@ void bl31_console_setup(void)
static console_16550_t console;
/* Initialize the console to provide early debug support */
console_16550_register(K3_USART_BASE_ADDRESS, K3_USART_CLK_SPEED,
console_16550_register(K3_USART_BASE, K3_USART_CLK_SPEED,
K3_USART_BAUD, &console);
}

3
plat/ti/k3/common/plat_common.mk
View File

@ -22,6 +22,9 @@ ERRATA_A53_836870 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
# Split out RO data into a non-executable section
SEPARATE_CODE_AND_RODATA := 1
# Leave the caches enabled on core powerdown path
TI_AM65X_WORKAROUND := 1
$(eval $(call add_define,TI_AM65X_WORKAROUND))

18
plat/ti/k3/include/platform_def.h
View File

@ -74,20 +74,14 @@
/*
* ARM-TF lives in SRAM, partition it here
*/
#define SHARED_RAM_BASE BL31_LIMIT
#define SHARED_RAM_SIZE 0x00001000
/*
*
* BL3-1 specific defines.
*
* Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM.
* Put BL3-1 at the base of the Trusted SRAM.
*/
#define BL31_BASE SEC_SRAM_BASE
#define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
#define BL31_SIZE SEC_SRAM_SIZE
#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
#define BL31_PROGBITS_LIMIT BL31_LIMIT
/*
* Defines the maximum number of translation tables that are allocated by the
@ -125,8 +119,8 @@
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
/* Platform default console definitions */
#ifndef K3_USART_BASE_ADDRESS
#define K3_USART_BASE_ADDRESS 0x02800000
#ifndef K3_USART_BASE
#define K3_USART_BASE 0x02800000
#endif
/* USART has a default size for address space */
@ -137,7 +131,7 @@
#endif
/* Crash console defaults */
#define CRASH_CONSOLE_BASE K3_USART_BASE_ADDRESS
#define CRASH_CONSOLE_BASE K3_USART_BASE
#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD