Merge changes from topic "k3-cleanups" into integration
* changes: ti: k3: common: Align elements of map region table ti: k3: common: Enable SEPARATE_CODE_AND_RODATA by default ti: k3: common: Remove shared RAM space ti: k3: common: Drop _ADDRESS from K3_USART_BASE to match other defines
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568bfb7b3f
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@ -21,8 +21,7 @@
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/* Table of regions to map using the MMU */
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/* Table of regions to map using the MMU */
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const mmap_region_t plat_k3_mmap[] = {
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const mmap_region_t plat_k3_mmap[] = {
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MAP_REGION_FLAT(SHARED_RAM_BASE, SHARED_RAM_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(K3_USART_BASE_ADDRESS, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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@ -100,13 +99,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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void bl31_plat_arch_setup(void)
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void bl31_plat_arch_setup(void)
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{
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{
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const mmap_region_t bl_regions[] = {
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const mmap_region_t bl_regions[] = {
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MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
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MAP_REGION_FLAT(BL31_START, BL31_END - BL31_START, MT_MEMORY | MT_RW | MT_SECURE),
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MT_MEMORY | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_RO | MT_SECURE),
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MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
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MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_END, MT_RO_DATA | MT_RO | MT_SECURE),
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MT_CODE | MT_SECURE),
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{ /* sentinel */ }
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MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_END,
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MT_RO_DATA | MT_SECURE),
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{0}
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};
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};
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setup_page_tables(bl_regions, plat_k3_mmap);
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setup_page_tables(bl_regions, plat_k3_mmap);
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@ -16,6 +16,6 @@ void bl31_console_setup(void)
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static console_16550_t console;
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static console_16550_t console;
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/* Initialize the console to provide early debug support */
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/* Initialize the console to provide early debug support */
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console_16550_register(K3_USART_BASE_ADDRESS, K3_USART_CLK_SPEED,
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console_16550_register(K3_USART_BASE, K3_USART_CLK_SPEED,
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K3_USART_BAUD, &console);
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K3_USART_BAUD, &console);
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}
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}
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@ -22,6 +22,9 @@ ERRATA_A53_836870 := 1
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ERRATA_A53_843419 := 1
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ERRATA_A53_843419 := 1
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ERRATA_A53_855873 := 1
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ERRATA_A53_855873 := 1
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# Split out RO data into a non-executable section
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SEPARATE_CODE_AND_RODATA := 1
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# Leave the caches enabled on core powerdown path
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# Leave the caches enabled on core powerdown path
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TI_AM65X_WORKAROUND := 1
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TI_AM65X_WORKAROUND := 1
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$(eval $(call add_define,TI_AM65X_WORKAROUND))
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$(eval $(call add_define,TI_AM65X_WORKAROUND))
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@ -74,20 +74,14 @@
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/*
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/*
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* ARM-TF lives in SRAM, partition it here
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* ARM-TF lives in SRAM, partition it here
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*/
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*
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#define SHARED_RAM_BASE BL31_LIMIT
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#define SHARED_RAM_SIZE 0x00001000
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/*
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* BL3-1 specific defines.
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* BL3-1 specific defines.
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*
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*
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* Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM.
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* Put BL3-1 at the base of the Trusted SRAM.
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*/
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*/
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#define BL31_BASE SEC_SRAM_BASE
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#define BL31_BASE SEC_SRAM_BASE
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#define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
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#define BL31_SIZE SEC_SRAM_SIZE
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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#define BL31_PROGBITS_LIMIT BL31_LIMIT
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/*
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/*
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* Defines the maximum number of translation tables that are allocated by the
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* Defines the maximum number of translation tables that are allocated by the
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@ -125,8 +119,8 @@
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/* Platform default console definitions */
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/* Platform default console definitions */
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#ifndef K3_USART_BASE_ADDRESS
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#ifndef K3_USART_BASE
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#define K3_USART_BASE_ADDRESS 0x02800000
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#define K3_USART_BASE 0x02800000
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#endif
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#endif
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/* USART has a default size for address space */
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/* USART has a default size for address space */
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@ -137,7 +131,7 @@
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#endif
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#endif
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/* Crash console defaults */
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/* Crash console defaults */
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#define CRASH_CONSOLE_BASE K3_USART_BASE_ADDRESS
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#define CRASH_CONSOLE_BASE K3_USART_BASE
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#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
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#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
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#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD
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#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD
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