rockchip/rk3399: save/restore watchdog register correctly
there are two fix for save/restore watchdog register: 1. watchdog plck will shutdown after secure_watchdog_disable(), so need to save register before it and restore after secure_watchdog_enable(). 2. need write 0x76 to cnt_restart to keep watchdog alive when restore watchdog register. Change-Id: I1f6fbceae22186e3b72a87df6332a110adf37479 Signed-off-by: Lin Huang <hl@rock-chips.com>
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@ -1319,10 +1319,14 @@ void wdt_register_restore(void)
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{
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{
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int i;
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int i;
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for (i = 0; i < 2; i++) {
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for (i = 1; i >= 0; i--) {
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mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]);
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mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]);
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mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]);
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mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]);
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}
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}
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/* write 0x76 to cnt_restart to keep watchdog alive */
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mmio_write_32(WDT0_BASE + 0x0c, 0x76);
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mmio_write_32(WDT1_BASE + 0x0c, 0x76);
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}
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}
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int rockchip_soc_sys_pwr_dm_suspend(void)
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int rockchip_soc_sys_pwr_dm_suspend(void)
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@ -1383,6 +1387,7 @@ int rockchip_soc_sys_pwr_dm_suspend(void)
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}
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}
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mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
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mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
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wdt_register_save();
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secure_watchdog_disable();
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secure_watchdog_disable();
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/*
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/*
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@ -1398,7 +1403,6 @@ int rockchip_soc_sys_pwr_dm_suspend(void)
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suspend_uart();
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suspend_uart();
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grf_register_save();
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grf_register_save();
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cru_register_save();
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cru_register_save();
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wdt_register_save();
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sram_save();
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sram_save();
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plat_rockchip_save_gpio();
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plat_rockchip_save_gpio();
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@ -1411,7 +1415,6 @@ int rockchip_soc_sys_pwr_dm_resume(void)
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uint32_t status = 0;
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uint32_t status = 0;
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plat_rockchip_restore_gpio();
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plat_rockchip_restore_gpio();
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wdt_register_restore();
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cru_register_restore();
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cru_register_restore();
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grf_register_restore();
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grf_register_restore();
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resume_uart();
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resume_uart();
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@ -1426,6 +1429,7 @@ int rockchip_soc_sys_pwr_dm_resume(void)
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secure_watchdog_enable();
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secure_watchdog_enable();
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secure_sgrf_init();
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secure_sgrf_init();
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secure_sgrf_ddr_rgn_init();
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secure_sgrf_ddr_rgn_init();
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wdt_register_restore();
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/* restore clk_ddrc_bpll_src_en gate */
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/* restore clk_ddrc_bpll_src_en gate */
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mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),
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mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),
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