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refactor(drivers/marvell/comphy-3700): move and add comment for COMPHY_RESERVED_REG 

The COMPHY_RESERVED_REG (offset 0x0E) is currently defined between
COMPHY_KVCO_CAL_CTRL (0x02) and COMPHY_DIG_LOOPBACK_EN (0x23).

But this register does not come from PHY lane register space. The
address 0x0E is not relative to PHY lane registers base address.

It only exists in the indirect register space, before PHY lane 2
registers (which start at address 0x200).

Move its definition in the header and add a comment.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie726384b980ace83d8ea327df09d928db74c2ab7
This commit is contained in:
Marek Behún 2021-12-02 20:04:57 +01:00
parent 66f07bd018
commit 580742d003
1 changed files with 9 additions and 3 deletions
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12
drivers/marvell/comphy/phy-comphy-3700.h
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@ -72,9 +72,6 @@ enum {
#define SPEED_PLL_MASK (0x3F << SPEED_PLL_OFFSET)
#define SPEED_PLL_VALUE_16 (0x10 << SPEED_PLL_OFFSET)
#define COMPHY_RESERVED_REG 0x0E
#define PHYCTRL_FRM_PIN_BIT BIT(13)
#define COMPHY_DIG_LOOPBACK_EN 0x23
#define DIG_LOOPBACK_EN_ADDR(unit) (COMPHY_DIG_LOOPBACK_EN * \
PHY_SHFT(unit))
@ -221,6 +218,15 @@ enum {
#define CFG_PM_RXDLOZ_WAIT_7_UNIT (7 << CFG_PM_RXDLOZ_WAIT_OFF)
#define CFG_PM_RXDLOZ_WAIT_12_UNIT (0xC << CFG_PM_RXDLOZ_WAIT_OFF)
/*
* This register is not from PHY lane register space. It only exists in the
* indirect register space, before the actual PHY lane 2 registers. So the
* offset is absolute, not relative to SATAPHY_LANE2_REG_BASE_OFFSET.
* It is used only for SATA PHY initialization.
*/
#define COMPHY_RESERVED_REG 0x0E
#define PHYCTRL_FRM_PIN_BIT BIT(13)
/* SGMII */
#define COMPHY_PHY_CFG1_OFFSET(lane) ((1 - (lane)) * 0x28)
#define PIN_PU_IVREF_BIT BIT(1)