TF-A: Add GICv4 extension for GIC driver
This patch adds support for GICv4 extension. New `GIC_ENABLE_V4_EXTN` option passed to gicv3.mk makefile was added, and enables GICv4 related changes when set to 1. This option defaults to 0. Change-Id: I30ebe1b7a98d3a54863900f37eda4589c707a288 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Alexei Fedorov
parent
8f3ad76614
commit
5875f2665d
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@ -693,6 +693,9 @@ makefile:
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functions. This is required for FVP platform which need to simulate GIC save
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and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.
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- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver.
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This option defaults to 0.
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- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended
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PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0.
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@ -8,6 +8,7 @@
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GICV3_IMPL ?= GIC500
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GICV3_IMPL_GIC600_MULTICHIP ?= 0
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GICV3_OVERRIDE_DISTIF_PWR_OPS ?= 0
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GIC_ENABLE_V4_EXTN ?= 0
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GIC_EXT_INTID ?= 0
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GICV3_SOURCES += drivers/arm/gic/v3/gicv3_main.c \
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@ -33,6 +34,10 @@ else
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$(error "Incorrect GICV3_IMPL value ${GICV3_IMPL}")
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endif
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# Set GICv4 extension
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$(eval $(call assert_boolean,GIC_ENABLE_V4_EXTN))
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$(eval $(call add_define,GIC_ENABLE_V4_EXTN))
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# Set support for extended PPI and SPI range
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$(eval $(call assert_boolean,GIC_EXT_INTID))
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$(eval $(call add_define,GIC_EXT_INTID))
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@ -116,12 +116,20 @@ void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
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(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
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#endif /* !__aarch64__ */
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/* The GIC version should be 3 */
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gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
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gic_version >>= PIDR2_ARCH_REV_SHIFT;
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gic_version &= PIDR2_ARCH_REV_MASK;
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assert(gic_version == ARCH_REV_GICV3);
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/* Check GIC version */
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#if GIC_ENABLE_V4_EXTN
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assert(gic_version == ARCH_REV_GICV4);
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/* GICv4 supports Direct Virtual LPI injection */
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assert((gicd_read_typer(plat_driver_data->gicd_base)
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& TYPER_DVIS) != 0);
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#else
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assert(gic_version == ARCH_REV_GICV3);
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#endif
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/*
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* Find out whether the GIC supports the GICv2 compatibility mode.
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* The ARE_S bit resets to 0 if supported
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@ -165,10 +173,9 @@ void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
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flush_dcache_range((uintptr_t)gicv3_driver_data,
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sizeof(*gicv3_driver_data));
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#endif
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INFO("GICv3 with%s legacy support detected."
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" ARM GICv3 driver initialized in EL3\n",
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(gicv2_compat == 0U) ? "" : "out");
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INFO("GICv%u with%s legacy support detected.\n", gic_version,
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(gicv2_compat == 0U) ? "" : "out");
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INFO("ARM GICv%u driver initialized in EL3\n", gic_version);
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}
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/*******************************************************************************
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -40,7 +40,7 @@
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#define GIC_HIGHEST_NS_PRIORITY U(0x80)
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/*******************************************************************************
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* GIC Distributor interface register offsets that are common to GICv3 & GICv2
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* Common GIC Distributor interface register offsets
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******************************************************************************/
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#define GICD_CTLR U(0x0)
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#define GICD_TYPER U(0x4)
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@ -61,19 +61,17 @@
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#define CTLR_ENABLE_G0_MASK U(0x1)
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#define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT)
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/*******************************************************************************
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* GIC Distributor interface register constants that are common to GICv3 & GICv2
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* Common GIC Distributor interface register constants
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******************************************************************************/
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#define PIDR2_ARCH_REV_SHIFT 4
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#define PIDR2_ARCH_REV_MASK U(0xf)
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/* GICv3 revision as reported by the PIDR2 register */
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#define ARCH_REV_GICV3 U(0x3)
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/* GICv2 revision as reported by the PIDR2 register */
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#define ARCH_REV_GICV2 U(0x2)
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/* GICv1 revision as reported by the PIDR2 register */
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/* GIC revision as reported by PIDR2.ArchRev register field */
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#define ARCH_REV_GICV1 U(0x1)
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#define ARCH_REV_GICV2 U(0x2)
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#define ARCH_REV_GICV3 U(0x3)
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#define ARCH_REV_GICV4 U(0x4)
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#define IGROUPR_SHIFT 5
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#define ISENABLER_SHIFT 5
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@ -151,9 +151,13 @@
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#define TYPER_ESPI_RANGE U(TYPER_ESPI_MASK << TYPER_ESPI_SHIFT)
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/*******************************************************************************
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* GICv3 and 3.1 Redistributor interface registers & constants
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* Common GIC Redistributor interface registers & constants
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******************************************************************************/
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#if GIC_ENABLE_V4_EXTN
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#define GICR_PCPUBASE_SHIFT 0x12
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#else
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#define GICR_PCPUBASE_SHIFT 0x11
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#endif
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#define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */
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#define GICR_CTLR U(0x0)
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#define GICR_IIDR U(0x04)
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