TF-A: Add GICv4 extension for GIC driver

This patch adds support for GICv4 extension.
New `GIC_ENABLE_V4_EXTN` option passed to gicv3.mk makefile
was added, and enables GICv4 related changes when set to 1.
This option defaults to 0.

Change-Id: I30ebe1b7a98d3a54863900f37eda4589c707a288
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

docs/getting_started/build-options.rst

@@ -693,6 +693,9 @@ makefile:
    functions. This is required for FVP platform which need to simulate GIC save
    and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.
 
+-  ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver.
+   This option defaults to 0.
+
 -  ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended
    PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0.
 

drivers/arm/gic/v3/gicv3.mk

@@ -8,6 +8,7 @@
 GICV3_IMPL			?=	GIC500
 GICV3_IMPL_GIC600_MULTICHIP	?=	0
 GICV3_OVERRIDE_DISTIF_PWR_OPS	?=	0
+GIC_ENABLE_V4_EXTN		?=	0
 GIC_EXT_INTID			?=	0
 
 GICV3_SOURCES	+=	drivers/arm/gic/v3/gicv3_main.c		\
@@ -33,6 +34,10 @@ else
 $(error "Incorrect GICV3_IMPL value ${GICV3_IMPL}")
 endif
 
+# Set GICv4 extension
+$(eval $(call assert_boolean,GIC_ENABLE_V4_EXTN))
+$(eval $(call add_define,GIC_ENABLE_V4_EXTN))
+
 # Set support for extended PPI and SPI range
 $(eval $(call assert_boolean,GIC_EXT_INTID))
 $(eval $(call add_define,GIC_EXT_INTID))

drivers/arm/gic/v3/gicv3_main.c

@@ -116,12 +116,20 @@ void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
 			(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
 #endif /* !__aarch64__ */
 
-	/* The GIC version should be 3 */
 	gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
 	gic_version >>= PIDR2_ARCH_REV_SHIFT;
 	gic_version &= PIDR2_ARCH_REV_MASK;
-	assert(gic_version == ARCH_REV_GICV3);
 
+	/* Check GIC version */
+#if GIC_ENABLE_V4_EXTN
+	assert(gic_version == ARCH_REV_GICV4);
+
+	/* GICv4 supports Direct Virtual LPI injection */
+	assert((gicd_read_typer(plat_driver_data->gicd_base)
+					& TYPER_DVIS) != 0);
+#else
+	assert(gic_version == ARCH_REV_GICV3);
+#endif
 	/*
 	 * Find out whether the GIC supports the GICv2 compatibility mode.
 	 * The ARE_S bit resets to 0 if supported
@@ -165,10 +173,9 @@ void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
 	flush_dcache_range((uintptr_t)gicv3_driver_data,
 		sizeof(*gicv3_driver_data));
 #endif
-
+	INFO("GICv%u with%s legacy support detected.\n", gic_version,
-	INFO("GICv3 with%s legacy support detected."
+				(gicv2_compat == 0U) ? "" : "out");
-			" ARM GICv3 driver initialized in EL3\n",
+	INFO("ARM GICv%u driver initialized in EL3\n", gic_version);
-			(gicv2_compat == 0U) ? "" : "out");
 }
 
 /*******************************************************************************

include/drivers/arm/gic_common.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -40,7 +40,7 @@
 #define GIC_HIGHEST_NS_PRIORITY		U(0x80)
 
 /*******************************************************************************
- * GIC Distributor interface register offsets that are common to GICv3 & GICv2
+ * Common GIC Distributor interface register offsets
  ******************************************************************************/
 #define GICD_CTLR		U(0x0)
 #define GICD_TYPER		U(0x4)
@@ -61,19 +61,17 @@
 #define CTLR_ENABLE_G0_MASK		U(0x1)
 #define CTLR_ENABLE_G0_BIT		BIT_32(CTLR_ENABLE_G0_SHIFT)
 
-
 /*******************************************************************************
- * GIC Distributor interface register constants that are common to GICv3 & GICv2
+ * Common GIC Distributor interface register constants
  ******************************************************************************/
 #define PIDR2_ARCH_REV_SHIFT	4
 #define PIDR2_ARCH_REV_MASK	U(0xf)
 
-/* GICv3 revision as reported by the PIDR2 register */
+/* GIC revision as reported by PIDR2.ArchRev register field */
-#define ARCH_REV_GICV3		U(0x3)
-/* GICv2 revision as reported by the PIDR2 register */
-#define ARCH_REV_GICV2		U(0x2)
-/* GICv1 revision as reported by the PIDR2 register */
 #define ARCH_REV_GICV1		U(0x1)
+#define ARCH_REV_GICV2		U(0x2)
+#define ARCH_REV_GICV3		U(0x3)
+#define ARCH_REV_GICV4		U(0x4)
 
 #define IGROUPR_SHIFT		5
 #define ISENABLER_SHIFT		5

include/drivers/arm/gicv3.h

@@ -151,9 +151,13 @@
 #define	TYPER_ESPI_RANGE	U(TYPER_ESPI_MASK << TYPER_ESPI_SHIFT)
 
 /*******************************************************************************
- * GICv3 and 3.1 Redistributor interface registers & constants
+ * Common GIC Redistributor interface registers & constants
  ******************************************************************************/
+#if GIC_ENABLE_V4_EXTN
+#define GICR_PCPUBASE_SHIFT	0x12
+#else
 #define GICR_PCPUBASE_SHIFT	0x11
+#endif
 #define GICR_SGIBASE_OFFSET	U(65536)	/* 64 KB */
 #define GICR_CTLR		U(0x0)
 #define GICR_IIDR		U(0x04)