stm32mp1: Add device tree files
Those device tree files are taken from STM32MP1 U-Boot and Linux. And they are updated to fit TF-A needs. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
This commit is contained in:
Yann Gautier
parent
964dfee1a2
commit
587f60fac5
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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/ {
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soc {
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ddr: ddr@0x5A003000{
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compatible = "st,stm32mp1-ddr";
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reg = <0x5A003000 0x550
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0x5A004000 0x234>;
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clocks = <&rcc AXIDCG>,
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<&rcc DDRC1>,
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<&rcc DDRC2>,
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<&rcc DDRPHYC>,
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<&rcc DDRCAPB>,
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<&rcc DDRPHYCAPB>;
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clock-names = "axidcg",
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"ddrc1",
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"ddrc2",
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"ddrphyc",
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"ddrcapb",
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"ddrphycapb";
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st,mem-name = DDR_MEM_NAME;
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st,mem-speed = <DDR_MEM_SPEED>;
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st,mem-size = <DDR_MEM_SIZE>;
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st,ctl-reg = <
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DDR_MSTR
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DDR_MRCTRL0
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DDR_MRCTRL1
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DDR_DERATEEN
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DDR_DERATEINT
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DDR_PWRCTL
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DDR_PWRTMG
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DDR_HWLPCTL
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DDR_RFSHCTL0
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DDR_RFSHCTL3
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DDR_CRCPARCTL0
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DDR_ZQCTL0
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DDR_DFITMG0
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DDR_DFITMG1
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DDR_DFILPCFG0
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DDR_DFIUPD0
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DDR_DFIUPD1
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DDR_DFIUPD2
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DDR_DFIPHYMSTR
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DDR_ODTMAP
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DDR_DBG0
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DDR_DBG1
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DDR_DBGCMD
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DDR_POISONCFG
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DDR_PCCFG
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>;
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st,ctl-timing = <
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DDR_RFSHTMG
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DDR_DRAMTMG0
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DDR_DRAMTMG1
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DDR_DRAMTMG2
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DDR_DRAMTMG3
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DDR_DRAMTMG4
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DDR_DRAMTMG5
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DDR_DRAMTMG6
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DDR_DRAMTMG7
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DDR_DRAMTMG8
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DDR_DRAMTMG14
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DDR_ODTCFG
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>;
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st,ctl-map = <
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DDR_ADDRMAP1
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DDR_ADDRMAP2
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DDR_ADDRMAP3
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DDR_ADDRMAP4
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DDR_ADDRMAP5
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DDR_ADDRMAP6
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DDR_ADDRMAP9
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DDR_ADDRMAP10
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DDR_ADDRMAP11
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>;
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st,ctl-perf = <
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DDR_SCHED
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DDR_SCHED1
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DDR_PERFHPR1
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DDR_PERFLPR1
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DDR_PERFWR1
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DDR_PCFGR_0
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DDR_PCFGW_0
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DDR_PCFGQOS0_0
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DDR_PCFGQOS1_0
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DDR_PCFGWQOS0_0
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DDR_PCFGWQOS1_0
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DDR_PCFGR_1
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DDR_PCFGW_1
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DDR_PCFGQOS0_1
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DDR_PCFGQOS1_1
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DDR_PCFGWQOS0_1
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DDR_PCFGWQOS1_1
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>;
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st,phy-reg = <
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DDR_PGCR
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DDR_ACIOCR
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DDR_DXCCR
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DDR_DSGCR
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DDR_DCR
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DDR_ODTCR
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DDR_ZQ0CR1
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DDR_DX0GCR
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DDR_DX1GCR
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DDR_DX2GCR
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DDR_DX3GCR
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>;
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st,phy-timing = <
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DDR_PTR0
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DDR_PTR1
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DDR_PTR2
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DDR_DTPR0
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DDR_DTPR1
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DDR_DTPR2
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DDR_MR0
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DDR_MR1
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DDR_MR2
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DDR_MR3
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>;
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st,phy-cal = <
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DDR_DX0DLLCR
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DDR_DX0DQTR
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DDR_DX0DQSTR
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DDR_DX1DLLCR
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DDR_DX1DQTR
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DDR_DX1DQSTR
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DDR_DX2DLLCR
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DDR_DX2DQTR
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DDR_DX2DQSTR
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DDR_DX3DLLCR
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DDR_DX3DQTR
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DDR_DX3DQSTR
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>;
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status = "okay";
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};
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};
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};
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@ -0,0 +1,121 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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/* STM32MP157C ED1 and ED2 BOARD configuration
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* 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
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* Reference used NT5CC256M16DP-DI from NANYA
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*
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* DDR type / Platform DDR3/3L
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* freq 533MHz
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* width 32
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* datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
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* DDR density 8
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* timing mode optimized
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* Scheduling/QoS options : type = 2
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* address mapping : RBC
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*/
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#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.39"
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#define DDR_MEM_SPEED 533
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#define DDR_MEM_SIZE 0x40000000
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#define DDR_MSTR 0x00040401
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#define DDR_MRCTRL0 0x00000010
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#define DDR_MRCTRL1 0x00000000
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#define DDR_DERATEEN 0x00000000
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#define DDR_DERATEINT 0x00800000
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#define DDR_PWRCTL 0x00000000
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#define DDR_PWRTMG 0x00400010
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#define DDR_HWLPCTL 0x00000000
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#define DDR_RFSHCTL0 0x00210000
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#define DDR_RFSHCTL3 0x00000000
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#define DDR_RFSHTMG 0x0081008B
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#define DDR_CRCPARCTL0 0x00000000
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#define DDR_DRAMTMG0 0x121B2414
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#define DDR_DRAMTMG1 0x000A041C
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#define DDR_DRAMTMG2 0x0608090F
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#define DDR_DRAMTMG3 0x0050400C
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#define DDR_DRAMTMG4 0x08040608
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#define DDR_DRAMTMG5 0x06060403
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#define DDR_DRAMTMG6 0x02020002
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#define DDR_DRAMTMG7 0x00000202
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#define DDR_DRAMTMG8 0x00001005
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#define DDR_DRAMTMG14 0x000000A0
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#define DDR_ZQCTL0 0xC2000040
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#define DDR_DFITMG0 0x02060105
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#define DDR_DFITMG1 0x00000202
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#define DDR_DFILPCFG0 0x07000000
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#define DDR_DFIUPD0 0xC0400003
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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#define DDR_ADDRMAP1 0x00080808
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x00000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x07070707
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#define DDR_ADDRMAP6 0x0F070707
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00001201
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#define DDR_SCHED1 0x00000000
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#define DDR_PERFHPR1 0x01000001
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#define DDR_PERFLPR1 0x08000200
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#define DDR_PERFWR1 0x08000400
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#define DDR_DBG0 0x00000000
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#define DDR_DBG1 0x00000000
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#define DDR_DBGCMD 0x00000000
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#define DDR_POISONCFG 0x00000000
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#define DDR_PCCFG 0x00000010
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#define DDR_PCFGR_0 0x00010000
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#define DDR_PCFGW_0 0x00000000
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#define DDR_PCFGQOS0_0 0x02100B03
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#define DDR_PCFGQOS1_0 0x00800100
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#define DDR_PCFGWQOS0_0 0x01100B03
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#define DDR_PCFGWQOS1_0 0x01000200
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#define DDR_PCFGR_1 0x00010000
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#define DDR_PCFGW_1 0x00000000
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#define DDR_PCFGQOS0_1 0x02100B03
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#define DDR_PCFGQOS1_1 0x00800000
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#define DDR_PCFGWQOS0_1 0x01100B03
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#define DDR_PCFGWQOS1_1 0x01000200
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#define DDR_PGCR 0x01442E02
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#define DDR_PTR0 0x0022AA5B
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#define DDR_PTR1 0x04841104
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#define DDR_PTR2 0x042DA068
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#define DDR_ACIOCR 0x10400812
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#define DDR_DXCCR 0x00000C40
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#define DDR_DSGCR 0xF200001F
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#define DDR_DCR 0x0000000B
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#define DDR_DTPR0 0x38D488D0
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#define DDR_DTPR1 0x098B00D8
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#define DDR_DTPR2 0x10023600
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#define DDR_MR0 0x00000840
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#define DDR_MR1 0x00000000
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#define DDR_MR2 0x00000208
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#define DDR_MR3 0x00000000
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#define DDR_ODTCR 0x00010000
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0DLLCR 0x40000000
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#define DDR_DX0DQTR 0xFFFFFFFF
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#define DDR_DX0DQSTR 0x3DB02000
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1DLLCR 0x40000000
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#define DDR_DX1DQTR 0xFFFFFFFF
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#define DDR_DX1DQSTR 0x3DB02000
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2DLLCR 0x40000000
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#define DDR_DX2DQTR 0xFFFFFFFF
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#define DDR_DX2DQSTR 0x3DB02000
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3DLLCR 0x40000000
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#define DDR_DX3DQTR 0xFFFFFFFF
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#define DDR_DX3DQSTR 0x3DB02000
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#include "stm32mp15-ddr.dtsi"
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@ -0,0 +1,250 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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/ {
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soc {
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pinctrl: pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x50002000 0xa400>;
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pins-are-numbered;
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gpioa: gpio@50002000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc GPIOA>;
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st,bank-name = "GPIOA";
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status = "disabled";
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};
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gpiob: gpio@50003000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&rcc GPIOB>;
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st,bank-name = "GPIOB";
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status = "disabled";
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};
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gpioc: gpio@50004000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x400>;
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clocks = <&rcc GPIOC>;
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st,bank-name = "GPIOC";
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status = "disabled";
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};
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gpiod: gpio@50005000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x400>;
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clocks = <&rcc GPIOD>;
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st,bank-name = "GPIOD";
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status = "disabled";
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};
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gpioe: gpio@50006000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x4000 0x400>;
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clocks = <&rcc GPIOE>;
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st,bank-name = "GPIOE";
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status = "disabled";
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};
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gpiof: gpio@50007000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000 0x400>;
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clocks = <&rcc GPIOF>;
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st,bank-name = "GPIOF";
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status = "disabled";
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};
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gpiog: gpio@50008000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x6000 0x400>;
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clocks = <&rcc GPIOG>;
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st,bank-name = "GPIOG";
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status = "disabled";
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};
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gpioh: gpio@50009000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x7000 0x400>;
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clocks = <&rcc GPIOH>;
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st,bank-name = "GPIOH";
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status = "disabled";
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};
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gpioi: gpio@5000a000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x8000 0x400>;
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clocks = <&rcc GPIOI>;
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st,bank-name = "GPIOI";
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status = "disabled";
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};
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gpioj: gpio@5000b000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x9000 0x400>;
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clocks = <&rcc GPIOJ>;
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st,bank-name = "GPIOJ";
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status = "disabled";
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};
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gpiok: gpio@5000c000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xa000 0x400>;
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clocks = <&rcc GPIOK>;
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st,bank-name = "GPIOK";
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status = "disabled";
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};
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uart4_pins_a: uart4@0 {
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pins1 {
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pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
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bias-disable;
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};
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};
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usart3_pins_a: usart3@0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
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<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
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<STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
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bias-disable;
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};
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};
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sdmmc1_b4_pins_a: sdmmc1-b4@0 {
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pins {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
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<STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
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<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
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slew-rate = <3>;
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drive-push-pull;
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bias-disable;
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};
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};
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sdmmc1_dir_pins_a: sdmmc1-dir@0 {
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pins1 {
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pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
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<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
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<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
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slew-rate = <3>;
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drive-push-pull;
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bias-pull-up;
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};
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pins2{
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pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
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bias-pull-up;
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};
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||||
};
|
||||
|
||||
sdmmc2_b4_pins_a: sdmmc2-b4@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
||||
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
||||
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
||||
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
|
||||
<STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
|
||||
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
||||
slew-rate = <3>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_d47_pins_a: sdmmc2-d47@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
|
||||
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
|
||||
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
|
||||
<STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
|
||||
slew-rate = <3>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pin-controller-z {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x54004000 0x400>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x400>;
|
||||
clocks = <&rcc GPIOZ>;
|
||||
st,bank-name = "GPIOZ";
|
||||
st,bank-ioport = <11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4_pins_a: i2c4@0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
|
||||
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,246 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c.dtsi"
|
||||
#include "stm32mp157caa-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C-ED1 pmic eval daughter";
|
||||
compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
|
||||
|
||||
chosen {
|
||||
bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram";
|
||||
stdout-path = "serial3:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
|
||||
pmic: stpmu1@33 {
|
||||
compatible = "st,stpmu1";
|
||||
reg = <0x33>;
|
||||
status = "okay";
|
||||
|
||||
st,main_control_register = <0x04>;
|
||||
st,vin_control_register = <0xc0>;
|
||||
st,usb_control_register = <0x30>;
|
||||
|
||||
regulators {
|
||||
compatible = "st,stpmu1-regulators";
|
||||
|
||||
v3v3: buck4 {
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-over-current-protection;
|
||||
regulator-initial-mode = <8>;
|
||||
|
||||
regulator-state-standby {
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
regulator-unchanged-in-suspend;
|
||||
regulator-mode = <8>;
|
||||
};
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
regulator-state-disk {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_sd: ldo5 {
|
||||
regulator-name = "vdd_sd";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-standby {
|
||||
regulator-suspend-microvolt = <2900000>;
|
||||
regulator-unchanged-in-suspend;
|
||||
};
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
regulator-state-disk {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
instance = <2>;
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
||||
broken-cd;
|
||||
st,dirpol;
|
||||
st,negedge;
|
||||
st,pin-ckin;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-ddr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
st,dirpol;
|
||||
st,negedge;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
resets = <&rcc UART4_R>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ATF Specific */
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
gpio0 = &gpioa;
|
||||
gpio1 = &gpiob;
|
||||
gpio2 = &gpioc;
|
||||
gpio3 = &gpiod;
|
||||
gpio4 = &gpioe;
|
||||
gpio5 = &gpiof;
|
||||
gpio6 = &gpiog;
|
||||
gpio7 = &gpioh;
|
||||
gpio8 = &gpioi;
|
||||
gpio9 = &gpioj;
|
||||
gpio10 = &gpiok;
|
||||
gpio25 = &gpioz;
|
||||
i2c3 = &i2c4;
|
||||
};
|
||||
|
||||
soc {
|
||||
stgen: stgen@5C008000 {
|
||||
compatible = "st,stm32-stgen";
|
||||
reg = <0x5C008000 0x1000>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* CLOCK init */
|
||||
&rcc {
|
||||
st,clksrc = <
|
||||
CLK_MPU_PLL1P
|
||||
CLK_AXI_PLL2P
|
||||
CLK_PLL12_HSE
|
||||
CLK_PLL3_HSE
|
||||
CLK_PLL4_HSE
|
||||
CLK_RTC_LSE
|
||||
CLK_MCO1_DISABLED
|
||||
CLK_MCO2_DISABLED
|
||||
>;
|
||||
|
||||
st,clkdiv = <
|
||||
1 /*MPU*/
|
||||
0 /*AXI*/
|
||||
1 /*APB1*/
|
||||
1 /*APB2*/
|
||||
1 /*APB3*/
|
||||
1 /*APB4*/
|
||||
2 /*APB5*/
|
||||
23 /*RTC*/
|
||||
0 /*MCO1*/
|
||||
0 /*MCO2*/
|
||||
>;
|
||||
|
||||
st,pkcs = <
|
||||
CLK_CKPER_HSE
|
||||
CLK_FMC_ACLK
|
||||
CLK_QSPI_ACLK
|
||||
CLK_ETH_DISABLED
|
||||
CLK_SDMMC12_PLL3R
|
||||
CLK_DSI_DSIPLL
|
||||
CLK_STGEN_HSE
|
||||
CLK_USBPHY_HSE
|
||||
CLK_SPI2S1_PLL3Q
|
||||
CLK_SPI2S23_PLL3Q
|
||||
CLK_SPI45_HSI
|
||||
CLK_SPI6_HSI
|
||||
CLK_I2C46_HSI
|
||||
CLK_SDMMC3_PLL3R
|
||||
CLK_USBO_USBPHY
|
||||
CLK_ADC_CKPER
|
||||
CLK_CEC_LSE
|
||||
CLK_I2C12_HSI
|
||||
CLK_I2C35_HSI
|
||||
CLK_UART1_HSI
|
||||
CLK_UART24_HSI
|
||||
CLK_UART35_HSI
|
||||
CLK_UART6_HSI
|
||||
CLK_UART78_HSI
|
||||
CLK_SPDIF_PLL3Q
|
||||
CLK_FDCAN_PLL4Q
|
||||
CLK_SAI1_PLL3Q
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_SAI3_PLL3Q
|
||||
CLK_SAI4_PLL3Q
|
||||
CLK_RNG1_CSI
|
||||
CLK_RNG2_CSI
|
||||
CLK_LPTIM1_PCLK1
|
||||
CLK_LPTIM23_PCLK3
|
||||
CLK_LPTIM45_PCLK3
|
||||
>;
|
||||
|
||||
/* VCO = 1300.0 MHz => P = 650 (CPU) */
|
||||
pll1: st,pll@0 {
|
||||
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
|
||||
frac = < 0x800 >;
|
||||
};
|
||||
|
||||
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
||||
pll2: st,pll@1 {
|
||||
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
|
||||
frac = < 0x1400 >;
|
||||
};
|
||||
|
||||
/* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */
|
||||
pll3: st,pll@2 {
|
||||
cfg = < 2 97 3 15 7 PQR(1,1,1) >;
|
||||
frac = < 0x9ba >;
|
||||
};
|
||||
|
||||
/* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
|
||||
pll4: st,pll@3 {
|
||||
cfg = < 5 126 8 8 8 PQR(1,1,1) >;
|
||||
};
|
||||
};
|
||||
|
||||
/delete-node/ &clk_csi;
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32mp157c-ed1.dts"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C-EV1 pmic eval daughter on eval mother";
|
||||
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
|
||||
|
||||
chosen {
|
||||
bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram";
|
||||
stdout-path = "serial3:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&usart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usart3_pins_a>;
|
||||
resets = <&rcc USART3_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,240 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
serial0 = &usart1;
|
||||
serial1 = &usart2;
|
||||
serial2 = &usart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
serial5 = &usart6;
|
||||
serial6 = &uart7;
|
||||
serial7 = &uart8;
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
clk_hsi: clk-hsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <64000000>;
|
||||
};
|
||||
|
||||
clk_lse: clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_lsi: clk-lsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
clk_csi: clk-csi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <4000000>;
|
||||
};
|
||||
|
||||
clk_i2s_ckin: i2s_ckin {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <64000000>;
|
||||
};
|
||||
|
||||
clk_dsi_phy: ck_dsi_phy {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
clk_usbo_48m: ck_usbo_48m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usart2: serial@4000e000 {
|
||||
compatible = "st,stm32h7-usart";
|
||||
reg = <0x4000e000 0x400>;
|
||||
clocks = <&rcc USART2_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart3: serial@4000f000 {
|
||||
compatible = "st,stm32h7-usart";
|
||||
reg = <0x4000f000 0x400>;
|
||||
clocks = <&rcc USART3_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@40010000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40010000 0x400>;
|
||||
clocks = <&rcc UART4_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@40011000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40011000 0x400>;
|
||||
clocks = <&rcc UART5_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
uart7: serial@40018000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40018000 0x400>;
|
||||
clocks = <&rcc UART7_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart8: serial@40019000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40019000 0x400>;
|
||||
clocks = <&rcc UART8_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart6: serial@44003000 {
|
||||
compatible = "st,stm32h7-usart";
|
||||
reg = <0x44003000 0x400>;
|
||||
clocks = <&rcc USART6_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc3: sdmmc@48004000 {
|
||||
compatible = "st,stm32-sdmmc2";
|
||||
reg = <0x48004000 0x400>, <0x48005000 0x400>;
|
||||
reg-names = "sdmmc", "delay";
|
||||
clocks = <&rcc SDMMC3_K>;
|
||||
resets = <&rcc SDMMC3_R>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcc: rcc@50000000 {
|
||||
compatible = "syscon", "st,stm32mp1-rcc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x50000000 0x1000>;
|
||||
};
|
||||
|
||||
rcc_reboot: rcc-reboot@50000000 {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&rcc>;
|
||||
offset = <0x404>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
rng1: rng@54003000 {
|
||||
compatible = "st,stm32-rng";
|
||||
reg = <0x54003000 0x400>;
|
||||
clocks = <&rcc RNG1_K>;
|
||||
resets = <&rcc RNG1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fmc_nand: fmc_nand@58002000 {
|
||||
compatible = "st,stm32mp1-fmc";
|
||||
reg = <0x58002000 0x1000>,
|
||||
<0x80000000 0x40000>,
|
||||
<0x81000000 0x40000>,
|
||||
<0x88000000 0x40000>,
|
||||
<0x89000000 0x40000>;
|
||||
clocks = <&rcc FMC_K>;
|
||||
resets = <&rcc FMC_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qspi: qspi@58003000 {
|
||||
compatible = "st,stm32f469-qspi";
|
||||
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
||||
clocks = <&rcc QSPI_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc1: sdmmc@58005000 {
|
||||
compatible = "st,stm32-sdmmc2";
|
||||
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
|
||||
reg-names = "sdmmc", "delay";
|
||||
clocks = <&rcc SDMMC1_K>;
|
||||
resets = <&rcc SDMMC1_R>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc2: sdmmc@58007000 {
|
||||
compatible = "st,stm32-sdmmc2";
|
||||
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
|
||||
reg-names = "sdmmc", "delay";
|
||||
clocks = <&rcc SDMMC2_K>;
|
||||
resets = <&rcc SDMMC2_R>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iwdg2: iwdg@5a002000 {
|
||||
compatible = "st,stm32mp1-iwdg";
|
||||
reg = <0x5a002000 0x400>;
|
||||
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
|
||||
clock-names = "pclk", "lsi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@5c000000 {
|
||||
compatible = "st,stm32h7-usart";
|
||||
reg = <0x5c000000 0x400>;
|
||||
clocks = <&rcc USART1_K>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@5c002000 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x5c002000 0x400>;
|
||||
clocks = <&rcc I2C4_K>;
|
||||
resets = <&rcc I2C4_R>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc: rtc@5c004000 {
|
||||
compatible = "st,stm32mp1-rtc";
|
||||
reg = <0x5c004000 0x400>;
|
||||
clocks = <&rcc RTCAPB>, <&rcc RTC>;
|
||||
clock-names = "pclk", "rtc_ck";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*/
|
||||
|
||||
#include "stm32mp157-pinctrl.dtsi"
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pin-controller {
|
||||
compatible = "st,stm32mp157caa-pinctrl";
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@5000b000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
};
|
||||
|
||||
gpiok: gpio@5000c000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pin-controller-z {
|
||||
compatible = "st,stm32mp157caa-z-pinctrl";
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Torgue Alexandre <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_STM32_PINFUNC_H
|
||||
#define _DT_BINDINGS_STM32_PINFUNC_H
|
||||
|
||||
/* define PIN modes */
|
||||
#define GPIO 0x0
|
||||
#define AF0 0x1
|
||||
#define AF1 0x2
|
||||
#define AF2 0x3
|
||||
#define AF3 0x4
|
||||
#define AF4 0x5
|
||||
#define AF5 0x6
|
||||
#define AF6 0x7
|
||||
#define AF7 0x8
|
||||
#define AF8 0x9
|
||||
#define AF9 0xa
|
||||
#define AF10 0xb
|
||||
#define AF11 0xc
|
||||
#define AF12 0xd
|
||||
#define AF13 0xe
|
||||
#define AF14 0xf
|
||||
#define AF15 0x10
|
||||
#define ANALOG 0x11
|
||||
|
||||
/* define Pins number*/
|
||||
#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
|
||||
|
||||
#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
|
||||
#define _DT_BINDINGS_STM32MP1_RESET_H_
|
||||
|
||||
#define LTDC_R 3072
|
||||
#define DSI_R 3076
|
||||
#define DDRPERFM_R 3080
|
||||
#define USBPHY_R 3088
|
||||
#define SPI6_R 3136
|
||||
#define I2C4_R 3138
|
||||
#define I2C6_R 3139
|
||||
#define USART1_R 3140
|
||||
#define STGEN_R 3156
|
||||
#define GPIOZ_R 3200
|
||||
#define CRYP1_R 3204
|
||||
#define HASH1_R 3205
|
||||
#define RNG1_R 3206
|
||||
#define AXIM_R 3216
|
||||
#define GPU_R 3269
|
||||
#define ETHMAC_R 3274
|
||||
#define FMC_R 3276
|
||||
#define QSPI_R 3278
|
||||
#define SDMMC1_R 3280
|
||||
#define SDMMC2_R 3281
|
||||
#define CRC1_R 3284
|
||||
#define USBH_R 3288
|
||||
#define MDMA_R 3328
|
||||
#define MCU_R 8225
|
||||
#define TIM2_R 19456
|
||||
#define TIM3_R 19457
|
||||
#define TIM4_R 19458
|
||||
#define TIM5_R 19459
|
||||
#define TIM6_R 19460
|
||||
#define TIM7_R 19461
|
||||
#define TIM12_R 16462
|
||||
#define TIM13_R 16463
|
||||
#define TIM14_R 16464
|
||||
#define LPTIM1_R 19465
|
||||
#define SPI2_R 19467
|
||||
#define SPI3_R 19468
|
||||
#define USART2_R 19470
|
||||
#define USART3_R 19471
|
||||
#define UART4_R 19472
|
||||
#define UART5_R 19473
|
||||
#define UART7_R 19474
|
||||
#define UART8_R 19475
|
||||
#define I2C1_R 19477
|
||||
#define I2C2_R 19478
|
||||
#define I2C3_R 19479
|
||||
#define I2C5_R 19480
|
||||
#define SPDIF_R 19482
|
||||
#define CEC_R 19483
|
||||
#define DAC12_R 19485
|
||||
#define MDIO_R 19847
|
||||
#define TIM1_R 19520
|
||||
#define TIM8_R 19521
|
||||
#define TIM15_R 19522
|
||||
#define TIM16_R 19523
|
||||
#define TIM17_R 19524
|
||||
#define SPI1_R 19528
|
||||
#define SPI4_R 19529
|
||||
#define SPI5_R 19530
|
||||
#define USART6_R 19533
|
||||
#define SAI1_R 19536
|
||||
#define SAI2_R 19537
|
||||
#define SAI3_R 19538
|
||||
#define DFSDM_R 19540
|
||||
#define FDCAN_R 19544
|
||||
#define LPTIM2_R 19584
|
||||
#define LPTIM3_R 19585
|
||||
#define LPTIM4_R 19586
|
||||
#define LPTIM5_R 19587
|
||||
#define SAI4_R 19592
|
||||
#define SYSCFG_R 19595
|
||||
#define VREF_R 19597
|
||||
#define TMPSENS_R 19600
|
||||
#define PMBCTRL_R 19601
|
||||
#define DMA1_R 19648
|
||||
#define DMA2_R 19649
|
||||
#define DMAMUX_R 19650
|
||||
#define ADC12_R 19653
|
||||
#define USBO_R 19656
|
||||
#define SDMMC3_R 19664
|
||||
#define CAMITF_R 19712
|
||||
#define CRYP2_R 19716
|
||||
#define HASH2_R 19717
|
||||
#define RNG2_R 19718
|
||||
#define CRC2_R 19719
|
||||
#define HSEM_R 19723
|
||||
#define MBOX_R 19724
|
||||
#define GPIOA_R 19776
|
||||
#define GPIOB_R 19777
|
||||
#define GPIOC_R 19778
|
||||
#define GPIOD_R 19779
|
||||
#define GPIOE_R 19780
|
||||
#define GPIOF_R 19781
|
||||
#define GPIOG_R 19782
|
||||
#define GPIOH_R 19783
|
||||
#define GPIOI_R 19784
|
||||
#define GPIOJ_R 19785
|
||||
#define GPIOK_R 19786
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
|
||||
Loading…
Reference in New Issue