spd: trusty : fix defects flagged by MISRA scan
Main Fixes: Use int32_t replace int [Rule 4.6] Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Force operands of an operator to the same type category [Rule 10.4] Fixed if statement conditional to be essentially boolean [Rule 14.4] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: I98caa330c371757eb2dfb9438448cb99115ed907 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This commit is contained in:
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591054a375
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@ -7,69 +7,68 @@
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#ifndef SMCALL_H
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#define SMCALL_H
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#define SMC_NUM_ENTITIES 64
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#define SMC_NUM_ARGS 4
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#define SMC_NUM_PARAMS (SMC_NUM_ARGS - 1)
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#define SMC_NUM_ENTITIES 64U
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#define SMC_NUM_ARGS 4U
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#define SMC_NUM_PARAMS (SMC_NUM_ARGS - 1U)
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#define SMC_IS_FASTCALL(smc_nr) ((smc_nr) & 0x80000000)
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#define SMC_IS_SMC64(smc_nr) ((smc_nr) & 0x40000000)
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#define SMC_ENTITY(smc_nr) (((smc_nr) & 0x3F000000) >> 24)
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#define SMC_FUNCTION(smc_nr) ((smc_nr) & 0x0000FFFF)
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#define SMC_IS_FASTCALL(smc_nr) ((smc_nr) & 0x80000000U)
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#define SMC_IS_SMC64(smc_nr) ((smc_nr) & 0x40000000U)
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#define SMC_ENTITY(smc_nr) (((smc_nr) & 0x3F000000U) >> 24U)
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#define SMC_FUNCTION(smc_nr) ((smc_nr) & 0x0000FFFFU)
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#define SMC_NR(entity, fn, fastcall, smc64) \
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(((((unsigned int) (fastcall)) & 0x1) << 31) | \
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(((smc64) & 0x1) << 30) | \
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(((entity) & 0x3F) << 24) | \
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((fn) & 0xFFFF) \
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)
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(((((uint32_t)(fastcall)) & 0x1U) << 31U) | \
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(((smc64) & 0x1U) << 30U) | \
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(((entity) & 0x3FU) << 24U) | \
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((fn) & 0xFFFFU))
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#define SMC_FASTCALL_NR(entity, fn) SMC_NR((entity), (fn), 1, 0)
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#define SMC_FASTCALL64_NR(entity, fn) SMC_NR((entity), (fn), 1, 1)
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#define SMC_YIELDCALL_NR(entity, fn) SMC_NR((entity), (fn), 0, 0)
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#define SMC_YIELDCALL64_NR(entity, fn) SMC_NR((entity), (fn), 0, 1)
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#define SMC_FASTCALL_NR(entity, fn) SMC_NR((entity), (fn), 1U, 0U)
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#define SMC_FASTCALL64_NR(entity, fn) SMC_NR((entity), (fn), 1U, 1U)
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#define SMC_YIELDCALL_NR(entity, fn) SMC_NR((entity), (fn), 0U, 0U)
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#define SMC_YIELDCALL64_NR(entity, fn) SMC_NR((entity), (fn), 0U, 1U)
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#define SMC_ENTITY_ARCH 0 /* ARM Architecture calls */
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#define SMC_ENTITY_CPU 1 /* CPU Service calls */
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#define SMC_ENTITY_SIP 2 /* SIP Service calls */
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#define SMC_ENTITY_OEM 3 /* OEM Service calls */
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#define SMC_ENTITY_STD 4 /* Standard Service calls */
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#define SMC_ENTITY_RESERVED 5 /* Reserved for future use */
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#define SMC_ENTITY_TRUSTED_APP 48 /* Trusted Application calls */
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#define SMC_ENTITY_TRUSTED_OS 50 /* Trusted OS calls */
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#define SMC_ENTITY_LOGGING 51 /* Used for secure -> nonsecure logging */
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#define SMC_ENTITY_SECURE_MONITOR 60 /* Trusted OS calls internal to secure monitor */
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#define SMC_ENTITY_ARCH 0U /* ARM Architecture calls */
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#define SMC_ENTITY_CPU 1U /* CPU Service calls */
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#define SMC_ENTITY_SIP 2U /* SIP Service calls */
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#define SMC_ENTITY_OEM 3U /* OEM Service calls */
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#define SMC_ENTITY_STD 4U /* Standard Service calls */
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#define SMC_ENTITY_RESERVED 5U /* Reserved for future use */
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#define SMC_ENTITY_TRUSTED_APP 48U /* Trusted Application calls */
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#define SMC_ENTITY_TRUSTED_OS 50U /* Trusted OS calls */
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#define SMC_ENTITY_LOGGING 51U /* Used for secure -> nonsecure logging */
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#define SMC_ENTITY_SECURE_MONITOR 60U /* Trusted OS calls internal to secure monitor */
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/* FC = Fast call, YC = Yielding call */
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#define SMC_YC_RESTART_LAST SMC_YIELDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0)
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#define SMC_YC_NOP SMC_YIELDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 1)
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#define SMC_YC_RESTART_LAST SMC_YIELDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0U)
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#define SMC_YC_NOP SMC_YIELDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 1U)
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/*
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* Return from secure os to non-secure os with return value in r1
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*/
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#define SMC_YC_NS_RETURN SMC_YIELDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0)
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#define SMC_YC_NS_RETURN SMC_YIELDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0U)
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#define SMC_FC_RESERVED SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0)
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#define SMC_FC_FIQ_EXIT SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 1)
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#define SMC_FC_REQUEST_FIQ SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 2)
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#define SMC_FC_GET_NEXT_IRQ SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 3)
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#define SMC_FC_FIQ_ENTER SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 4)
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#define SMC_FC_RESERVED SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0U)
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#define SMC_FC_FIQ_EXIT SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 1U)
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#define SMC_FC_REQUEST_FIQ SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 2U)
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#define SMC_FC_GET_NEXT_IRQ SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 3U)
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#define SMC_FC_FIQ_ENTER SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 4U)
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#define SMC_FC64_SET_FIQ_HANDLER SMC_FASTCALL64_NR(SMC_ENTITY_SECURE_MONITOR, 5)
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#define SMC_FC64_GET_FIQ_REGS SMC_FASTCALL64_NR (SMC_ENTITY_SECURE_MONITOR, 6)
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#define SMC_FC64_SET_FIQ_HANDLER SMC_FASTCALL64_NR(SMC_ENTITY_SECURE_MONITOR, 5U)
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#define SMC_FC64_GET_FIQ_REGS SMC_FASTCALL64_NR (SMC_ENTITY_SECURE_MONITOR, 6U)
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#define SMC_FC_CPU_SUSPEND SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 7)
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#define SMC_FC_CPU_RESUME SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 8)
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#define SMC_FC_CPU_SUSPEND SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 7U)
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#define SMC_FC_CPU_RESUME SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 8U)
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#define SMC_FC_AARCH_SWITCH SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 9)
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#define SMC_FC_GET_VERSION_STR SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 10)
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#define SMC_FC_AARCH_SWITCH SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 9U)
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#define SMC_FC_GET_VERSION_STR SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 10U)
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/* Trusted OS entity calls */
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#define SMC_YC_VIRTIO_GET_DESCR SMC_YIELDCALL_NR(SMC_ENTITY_TRUSTED_OS, 20)
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#define SMC_YC_VIRTIO_START SMC_YIELDCALL_NR(SMC_ENTITY_TRUSTED_OS, 21)
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#define SMC_YC_VIRTIO_STOP SMC_YIELDCALL_NR(SMC_ENTITY_TRUSTED_OS, 22)
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#define SMC_YC_VIRTIO_GET_DESCR SMC_YIELDCALL_NR(SMC_ENTITY_TRUSTED_OS, 20U)
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#define SMC_YC_VIRTIO_START SMC_YIELDCALL_NR(SMC_ENTITY_TRUSTED_OS, 21U)
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#define SMC_YC_VIRTIO_STOP SMC_YIELDCALL_NR(SMC_ENTITY_TRUSTED_OS, 22U)
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#define SMC_YC_VDEV_RESET SMC_YIELDCALL_NR(SMC_ENTITY_TRUSTED_OS, 23)
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#define SMC_YC_VDEV_KICK_VQ SMC_YIELDCALL_NR(SMC_ENTITY_TRUSTED_OS, 24)
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#define SMC_YC_SET_ROT_PARAMS SMC_YIELDCALL_NR(SMC_ENTITY_TRUSTED_OS, 65535)
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#define SMC_YC_VDEV_RESET SMC_YIELDCALL_NR(SMC_ENTITY_TRUSTED_OS, 23U)
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#define SMC_YC_VDEV_KICK_VQ SMC_YIELDCALL_NR(SMC_ENTITY_TRUSTED_OS, 24U)
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#define SMC_YC_SET_ROT_PARAMS SMC_YIELDCALL_NR(SMC_ENTITY_TRUSTED_OS, 65535U)
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#endif /* SMCALL_H */
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@ -21,7 +21,10 @@
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#include "smcall.h"
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/* macro to check if Hypervisor is enabled in the HCR_EL2 register */
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#define HYP_ENABLE_FLAG 0x286001
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#define HYP_ENABLE_FLAG 0x286001U
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/* length of Trusty's input parameters (in bytes) */
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#define TRUSTY_PARAMS_LEN_BYTES (4096U * 2)
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struct trusty_stack {
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uint8_t space[PLATFORM_STACK_SIZE] __aligned(16);
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@ -32,7 +35,7 @@ struct trusty_cpu_ctx {
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cpu_context_t cpu_ctx;
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void *saved_sp;
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uint32_t saved_security_state;
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int fiq_handler_active;
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int32_t fiq_handler_active;
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uint64_t fiq_handler_pc;
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uint64_t fiq_handler_cpsr;
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uint64_t fiq_handler_sp;
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@ -43,7 +46,7 @@ struct trusty_cpu_ctx {
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struct trusty_stack secure_stack;
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};
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struct args {
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struct smc_args {
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uint64_t r0;
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uint64_t r1;
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uint64_t r2;
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@ -56,8 +59,8 @@ struct args {
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static struct trusty_cpu_ctx trusty_cpu_ctx[PLATFORM_CORE_COUNT];
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struct args trusty_init_context_stack(void **sp, void *new_stack);
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struct args trusty_context_switch_helper(void **sp, void *smc_params);
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struct smc_args trusty_init_context_stack(void **sp, void *new_stack);
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struct smc_args trusty_context_switch_helper(void **sp, void *smc_params);
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static uint32_t current_vmid;
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@ -66,37 +69,37 @@ static struct trusty_cpu_ctx *get_trusty_ctx(void)
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return &trusty_cpu_ctx[plat_my_core_pos()];
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}
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static uint32_t is_hypervisor_mode(void)
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static bool is_hypervisor_mode(void)
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{
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uint64_t hcr = read_hcr();
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return !!(hcr & HYP_ENABLE_FLAG);
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return ((hcr & HYP_ENABLE_FLAG) != 0U) ? true : false;
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}
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static struct args trusty_context_switch(uint32_t security_state, uint64_t r0,
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static struct smc_args trusty_context_switch(uint32_t security_state, uint64_t r0,
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uint64_t r1, uint64_t r2, uint64_t r3)
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{
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struct args ret;
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struct smc_args args, ret_args;
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struct trusty_cpu_ctx *ctx = get_trusty_ctx();
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struct trusty_cpu_ctx *ctx_smc;
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assert(ctx->saved_security_state != security_state);
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ret.r7 = 0;
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args.r7 = 0;
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if (is_hypervisor_mode()) {
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/* According to the ARM DEN0028A spec, VMID is stored in x7 */
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ctx_smc = cm_get_context(NON_SECURE);
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assert(ctx_smc);
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ret.r7 = SMC_GET_GP(ctx_smc, CTX_GPREG_X7);
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assert(ctx_smc != NULL);
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args.r7 = SMC_GET_GP(ctx_smc, CTX_GPREG_X7);
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}
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/* r4, r5, r6 reserved for future use. */
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ret.r6 = 0;
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ret.r5 = 0;
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ret.r4 = 0;
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ret.r3 = r3;
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ret.r2 = r2;
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ret.r1 = r1;
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ret.r0 = r0;
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args.r6 = 0;
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args.r5 = 0;
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args.r4 = 0;
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args.r3 = r3;
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args.r2 = r2;
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args.r1 = r1;
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args.r0 = r0;
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/*
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* To avoid the additional overhead in PSCI flow, skip FP context
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cm_el1_sysregs_context_save(security_state);
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ctx->saved_security_state = security_state;
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ret = trusty_context_switch_helper(&ctx->saved_sp, &ret);
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ret_args = trusty_context_switch_helper(&ctx->saved_sp, &args);
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assert(ctx->saved_security_state == !security_state);
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assert(ctx->saved_security_state == ((security_state == 0U) ? 1U : 0U));
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cm_el1_sysregs_context_restore(security_state);
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if (r0 != SMC_FC_CPU_SUSPEND && r0 != SMC_FC_CPU_RESUME)
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@ -119,7 +122,7 @@ static struct args trusty_context_switch(uint32_t security_state, uint64_t r0,
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cm_set_next_eret_context(security_state);
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return ret;
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return ret_args;
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}
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static uint64_t trusty_fiq_handler(uint32_t id,
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void *handle,
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void *cookie)
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{
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struct args ret;
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struct smc_args ret;
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struct trusty_cpu_ctx *ctx = get_trusty_ctx();
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assert(!is_caller_secure(flags));
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ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_ENTER, 0, 0, 0);
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if (ret.r0) {
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if (ret.r0 != 0U) {
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SMC_RET0(handle);
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}
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if (ctx->fiq_handler_active) {
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if (ctx->fiq_handler_active != 0) {
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INFO("%s: fiq handler already active\n", __func__);
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SMC_RET0(handle);
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}
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ctx->fiq_handler_active = 1;
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memcpy(&ctx->fiq_gpregs, get_gpregs_ctx(handle), sizeof(ctx->fiq_gpregs));
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(void)memcpy(&ctx->fiq_gpregs, get_gpregs_ctx(handle), sizeof(ctx->fiq_gpregs));
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ctx->fiq_pc = SMC_GET_EL3(handle, CTX_ELR_EL3);
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ctx->fiq_cpsr = SMC_GET_EL3(handle, CTX_SPSR_EL3);
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ctx->fiq_sp_el1 = read_ctx_reg(get_sysregs_ctx(handle), CTX_SP_EL1);
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write_ctx_reg(get_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_handler_sp);
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cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_handler_pc, ctx->fiq_handler_cpsr);
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cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_handler_pc, (uint32_t)ctx->fiq_handler_cpsr);
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SMC_RET0(handle);
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}
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{
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struct trusty_cpu_ctx *ctx;
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if (cpu >= PLATFORM_CORE_COUNT) {
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if (cpu >= (uint64_t)PLATFORM_CORE_COUNT) {
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ERROR("%s: cpu %lld >= %d\n", __func__, cpu, PLATFORM_CORE_COUNT);
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return SM_ERR_INVALID_PARAMETERS;
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return (uint64_t)SM_ERR_INVALID_PARAMETERS;
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}
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ctx = &trusty_cpu_ctx[cpu];
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@ -182,16 +185,16 @@ static uint64_t trusty_get_fiq_regs(void *handle)
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static uint64_t trusty_fiq_exit(void *handle, uint64_t x1, uint64_t x2, uint64_t x3)
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{
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struct args ret;
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struct smc_args ret;
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struct trusty_cpu_ctx *ctx = get_trusty_ctx();
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if (!ctx->fiq_handler_active) {
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if (ctx->fiq_handler_active == 0) {
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NOTICE("%s: fiq handler not active\n", __func__);
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SMC_RET1(handle, SM_ERR_INVALID_PARAMETERS);
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SMC_RET1(handle, (uint64_t)SM_ERR_INVALID_PARAMETERS);
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}
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ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_EXIT, 0, 0, 0);
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if (ret.r0 != 1) {
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if (ret.r0 != 1U) {
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INFO("%s(%p) SMC_FC_FIQ_EXIT returned unexpected value, %lld\n",
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__func__, handle, ret.r0);
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}
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@ -205,10 +208,10 @@ static uint64_t trusty_fiq_exit(void *handle, uint64_t x1, uint64_t x2, uint64_t
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* x1-x4 and x8-x17 need to be restored here because smc_handler64
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* corrupts them (el1 code also restored them).
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*/
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memcpy(get_gpregs_ctx(handle), &ctx->fiq_gpregs, sizeof(ctx->fiq_gpregs));
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(void)memcpy(get_gpregs_ctx(handle), &ctx->fiq_gpregs, sizeof(ctx->fiq_gpregs));
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ctx->fiq_handler_active = 0;
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write_ctx_reg(get_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_sp_el1);
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cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_pc, ctx->fiq_cpsr);
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cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_pc, (uint32_t)ctx->fiq_cpsr);
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SMC_RET0(handle);
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}
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@ -222,8 +225,8 @@ static uintptr_t trusty_smc_handler(uint32_t smc_fid,
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void *handle,
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u_register_t flags)
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{
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struct args ret;
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uint32_t vmid = 0;
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struct smc_args ret;
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uint32_t vmid = 0U;
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entry_point_info_t *ep_info = bl31_plat_get_next_image_ep_info(SECURE);
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/*
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@ -231,10 +234,12 @@ static uintptr_t trusty_smc_handler(uint32_t smc_fid,
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* Verified Boot is not even supported and returning success here
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* would not compromise the boot process.
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*/
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if (!ep_info && (smc_fid == SMC_YC_SET_ROT_PARAMS)) {
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if ((ep_info == NULL) && (smc_fid == SMC_YC_SET_ROT_PARAMS)) {
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SMC_RET1(handle, 0);
|
||||
} else if (!ep_info) {
|
||||
} else if (ep_info == NULL) {
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
} else {
|
||||
; /* do nothing */
|
||||
}
|
||||
|
||||
if (is_caller_secure(flags)) {
|
||||
|
@ -279,12 +284,11 @@ static uintptr_t trusty_smc_handler(uint32_t smc_fid,
|
|||
|
||||
static int32_t trusty_init(void)
|
||||
{
|
||||
void el3_exit(void);
|
||||
entry_point_info_t *ep_info;
|
||||
struct args zero_args = {0};
|
||||
struct smc_args zero_args = {0};
|
||||
struct trusty_cpu_ctx *ctx = get_trusty_ctx();
|
||||
uint32_t cpu = plat_my_core_pos();
|
||||
int reg_width = GET_RW(read_ctx_reg(get_el3state_ctx(&ctx->cpu_ctx),
|
||||
uint64_t reg_width = GET_RW(read_ctx_reg(get_el3state_ctx(&ctx->cpu_ctx),
|
||||
CTX_SPSR_EL3));
|
||||
|
||||
/*
|
||||
|
@ -292,7 +296,7 @@ static int32_t trusty_init(void)
|
|||
* failure.
|
||||
*/
|
||||
ep_info = bl31_plat_get_next_image_ep_info(SECURE);
|
||||
assert(ep_info);
|
||||
assert(ep_info != NULL);
|
||||
|
||||
fpregs_context_save(get_fpregs_ctx(cm_get_context(NON_SECURE)));
|
||||
cm_el1_sysregs_context_save(NON_SECURE);
|
||||
|
@ -304,7 +308,7 @@ static int32_t trusty_init(void)
|
|||
* Adjust secondary cpu entry point for 32 bit images to the
|
||||
* end of exception vectors
|
||||
*/
|
||||
if ((cpu != 0) && (reg_width == MODE_RW_32)) {
|
||||
if ((cpu != 0U) && (reg_width == MODE_RW_32)) {
|
||||
INFO("trusty: cpu %d, adjust entry point to 0x%lx\n",
|
||||
cpu, ep_info->pc + (1U << 5));
|
||||
cm_set_elr_el3(SECURE, ep_info->pc + (1U << 5));
|
||||
|
@ -314,10 +318,10 @@ static int32_t trusty_init(void)
|
|||
fpregs_context_restore(get_fpregs_ctx(cm_get_context(SECURE)));
|
||||
cm_set_next_eret_context(SECURE);
|
||||
|
||||
ctx->saved_security_state = ~0; /* initial saved state is invalid */
|
||||
trusty_init_context_stack(&ctx->saved_sp, &ctx->secure_stack.end);
|
||||
ctx->saved_security_state = ~0U; /* initial saved state is invalid */
|
||||
(void)trusty_init_context_stack(&ctx->saved_sp, &ctx->secure_stack.end);
|
||||
|
||||
trusty_context_switch_helper(&ctx->saved_sp, &zero_args);
|
||||
(void)trusty_context_switch_helper(&ctx->saved_sp, &zero_args);
|
||||
|
||||
cm_el1_sysregs_context_restore(NON_SECURE);
|
||||
fpregs_context_restore(get_fpregs_ctx(cm_get_context(NON_SECURE)));
|
||||
|
@ -328,10 +332,10 @@ static int32_t trusty_init(void)
|
|||
|
||||
static void trusty_cpu_suspend(uint32_t off)
|
||||
{
|
||||
struct args ret;
|
||||
struct smc_args ret;
|
||||
|
||||
ret = trusty_context_switch(NON_SECURE, SMC_FC_CPU_SUSPEND, off, 0, 0);
|
||||
if (ret.r0 != 0) {
|
||||
if (ret.r0 != 0U) {
|
||||
INFO("%s: cpu %d, SMC_FC_CPU_SUSPEND returned unexpected value, %lld\n",
|
||||
__func__, plat_my_core_pos(), ret.r0);
|
||||
}
|
||||
|
@ -339,10 +343,10 @@ static void trusty_cpu_suspend(uint32_t off)
|
|||
|
||||
static void trusty_cpu_resume(uint32_t on)
|
||||
{
|
||||
struct args ret;
|
||||
struct smc_args ret;
|
||||
|
||||
ret = trusty_context_switch(NON_SECURE, SMC_FC_CPU_RESUME, on, 0, 0);
|
||||
if (ret.r0 != 0) {
|
||||
if (ret.r0 != 0U) {
|
||||
INFO("%s: cpu %d, SMC_FC_CPU_RESUME returned unexpected value, %lld\n",
|
||||
__func__, plat_my_core_pos(), ret.r0);
|
||||
}
|
||||
|
@ -359,8 +363,8 @@ static void trusty_cpu_on_finish_handler(u_register_t unused)
|
|||
{
|
||||
struct trusty_cpu_ctx *ctx = get_trusty_ctx();
|
||||
|
||||
if (!ctx->saved_sp) {
|
||||
trusty_init();
|
||||
if (ctx->saved_sp == NULL) {
|
||||
(void)trusty_init();
|
||||
} else {
|
||||
trusty_cpu_resume(1);
|
||||
}
|
||||
|
@ -398,12 +402,12 @@ static int32_t trusty_setup(void)
|
|||
entry_point_info_t *ep_info;
|
||||
uint32_t instr;
|
||||
uint32_t flags;
|
||||
int ret;
|
||||
int32_t ret;
|
||||
bool aarch32 = false;
|
||||
|
||||
/* Get trusty's entry point info */
|
||||
ep_info = bl31_plat_get_next_image_ep_info(SECURE);
|
||||
if (!ep_info) {
|
||||
if (ep_info == NULL) {
|
||||
INFO("Trusty image missing.\n");
|
||||
return -1;
|
||||
}
|
||||
|
@ -444,8 +448,9 @@ static int32_t trusty_setup(void)
|
|||
ret = register_interrupt_type_handler(INTR_TYPE_S_EL1,
|
||||
trusty_fiq_handler,
|
||||
flags);
|
||||
if (ret)
|
||||
if (ret != 0) {
|
||||
ERROR("trusty: failed to register fiq handler, ret = %d\n", ret);
|
||||
}
|
||||
|
||||
if (aarch32) {
|
||||
entry_point_info_t *ns_ep_info;
|
||||
|
|
Loading…
Reference in New Issue