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Merge pull request #1415 from antonio-nino-diaz-arm/an/spm-fixes 

Minor fixes to SPM
This commit is contained in:
Dimitris Papastamos 2018-06-14 14:33:13 +01:00 committed by GitHub
parent f3a5e3d6ec d801a1d035
commit 59c4346383
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 74 additions and 76 deletions
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7
bl31/bl31.ld.S
View File

@ -221,13 +221,6 @@ SECTIONS
* tables library.
*/
xlat_table (NOLOAD) : {
#if ENABLE_SPM
__SP_IMAGE_XLAT_TABLES_START__ = .;
*secure_partition*.o(xlat_table)
/* Make sure that the rest of the page is empty. */
. = NEXT(PAGE_SIZE);
__SP_IMAGE_XLAT_TABLES_END__ = .;
#endif
*(xlat_table)
} >RAM

5
include/lib/xlat_tables/xlat_mmu_helpers.h
View File

@ -43,6 +43,8 @@
#ifndef __ASSEMBLY__
#include <sys/types.h>
#ifdef AARCH32
/* AArch32 specific translation table API */
void enable_mmu_secure(unsigned int flags);
@ -52,6 +54,9 @@ void enable_mmu_el1(unsigned int flags);
void enable_mmu_el3(unsigned int flags);
#endif /* AARCH32 */
int xlat_arch_is_granule_size_supported(size_t size);
size_t xlat_arch_get_max_supported_granule_size(void);
#endif /* __ASSEMBLY__ */
#endif /* __XLAT_MMU_HELPERS_H__ */

8
include/plat/arm/common/arm_def.h
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@ -245,13 +245,7 @@
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#if ENABLE_SPM && defined(IMAGE_BL31)
# if USE_COHERENT_MEM
# define ARM_BL_REGIONS 5
# else
# define ARM_BL_REGIONS 4
# endif
#elif USE_COHERENT_MEM
#if USE_COHERENT_MEM
# define ARM_BL_REGIONS 4
#else
# define ARM_BL_REGIONS 3

9
include/services/secure_partition.h
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@ -7,18 +7,9 @@
#ifndef __SECURE_PARTITION_H__
#define __SECURE_PARTITION_H__
#include <bl_common.h>
#include <types.h>
#include <utils_def.h>
/* Import linker symbols */
IMPORT_SYM(uintptr_t, __SP_IMAGE_XLAT_TABLES_START__, SP_IMAGE_XLAT_TABLES_START);
IMPORT_SYM(uintptr_t, __SP_IMAGE_XLAT_TABLES_END__, SP_IMAGE_XLAT_TABLES_END);
/* Definitions */
#define SP_IMAGE_XLAT_TABLES_SIZE \
(SP_IMAGE_XLAT_TABLES_END - SP_IMAGE_XLAT_TABLES_START)
/*
* Flags used by the secure_partition_mp_info structure to describe the
* characteristics of a cpu. Only a single flag is defined at the moment to

17
lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
View File

@ -18,6 +18,23 @@
#error ARMv7 target does not support LPAE MMU descriptors
#endif
/*
* Returns 1 if the provided granule size is supported, 0 otherwise.
*/
int xlat_arch_is_granule_size_supported(size_t size)
{
/*
* The Trusted Firmware uses long descriptor translation table format,
* which supports 4 KiB pages only.
*/
return (size == (4U * 1024U));
}
size_t xlat_arch_get_max_supported_granule_size(void)
{
return 4U * 1024U;
}
#if ENABLE_ASSERTIONS
unsigned long long xlat_arch_get_max_supported_pa(void)
{

36
lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
View File

@ -16,6 +16,42 @@
#include <xlat_tables_v2.h>
#include "../xlat_tables_private.h"
/*
* Returns 1 if the provided granule size is supported, 0 otherwise.
*/
int xlat_arch_is_granule_size_supported(size_t size)
{
u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1();
if (size == (4U * 1024U)) {
return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) &
ID_AA64MMFR0_EL1_TGRAN4_MASK) ==
ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED;
} else if (size == (16U * 1024U)) {
return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) &
ID_AA64MMFR0_EL1_TGRAN16_MASK) ==
ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED;
} else if (size == (64U * 1024U)) {
return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) &
ID_AA64MMFR0_EL1_TGRAN64_MASK) ==
ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED;
}
return 0;
}
size_t xlat_arch_get_max_supported_granule_size(void)
{
if (xlat_arch_is_granule_size_supported(64U * 1024U)) {
return 64U * 1024U;
} else if (xlat_arch_is_granule_size_supported(16U * 1024U)) {
return 16U * 1024U;
} else {
assert(xlat_arch_is_granule_size_supported(4U * 1024U));
return 4U * 1024U;
}
}
unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr)
{
/* Physical address can't exceed 48 bits */

8
plat/arm/common/arm_common.c
View File

@ -81,14 +81,6 @@ void arm_setup_page_tables(uintptr_t total_base,
MT_DEVICE | MT_RW | MT_SECURE);
#endif
#if ENABLE_SPM && defined(IMAGE_BL31)
/* The address of the following region is calculated by the linker. */
mmap_add_region(SP_IMAGE_XLAT_TABLES_START,
SP_IMAGE_XLAT_TABLES_START,
SP_IMAGE_XLAT_TABLES_SIZE,
MT_MEMORY | MT_RW | MT_SECURE);
#endif
/* Now (re-)map the platform-specific memory regions */
mmap_add(plat_arm_get_mmap());

60
services/std_svc/spm/sp_setup.c
View File

@ -33,16 +33,11 @@ void spm_sp_setup(sp_context_t *sp_ctx)
entry_point_info_t ep_info = {0};
SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
/* Setup entrypoint and SPSR */
ep_info.pc = BL32_BASE;
ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS);
cm_setup_context(ctx, &ep_info);
/*
* General-Purpose registers
* -------------------------
*/
/*
* X0: Virtual address of a buffer shared between EL3 and Secure EL0.
* The buffer will be mapped in the Secure EL1 translation regime
@ -55,12 +50,14 @@ void spm_sp_setup(sp_context_t *sp_ctx)
*
* X3: cookie value (Implementation Defined)
*
* X4 to X30 = 0 (already done by cm_init_my_context())
* X4 to X7 = 0
*/
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, PLAT_SPM_BUF_BASE);
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, PLAT_SPM_BUF_SIZE);
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, PLAT_SPM_COOKIE_0);
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, PLAT_SPM_COOKIE_1);
ep_info.args.arg0 = PLAT_SPM_BUF_BASE;
ep_info.args.arg1 = PLAT_SPM_BUF_SIZE;
ep_info.args.arg2 = PLAT_SPM_COOKIE_0;
ep_info.args.arg3 = PLAT_SPM_COOKIE_1;
cm_setup_context(ctx, &ep_info);
/*
* SP_EL0: A non-zero value will indicate to the SP that the SPM has
@ -78,45 +75,18 @@ void spm_sp_setup(sp_context_t *sp_ctx)
#if ENABLE_ASSERTIONS
/* Get max granularity supported by the platform. */
unsigned int max_granule = xlat_arch_get_max_supported_granule_size();
u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1();
VERBOSE("Max translation granule size supported: %u KiB\n",
max_granule / 1024U);
int tgran64_supported =
((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) &
ID_AA64MMFR0_EL1_TGRAN64_MASK) ==
ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED;
int tgran16_supported =
((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) &
ID_AA64MMFR0_EL1_TGRAN16_MASK) ==
ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED;
int tgran4_supported =
((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) &
ID_AA64MMFR0_EL1_TGRAN4_MASK) ==
ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED;
uintptr_t max_granule_size;
if (tgran64_supported) {
max_granule_size = 64 * 1024;
} else if (tgran16_supported) {
max_granule_size = 16 * 1024;
} else {
assert(tgran4_supported);
max_granule_size = 4 * 1024;
}
VERBOSE("Max translation granule supported: %lu KiB\n",
max_granule_size / 1024);
uintptr_t max_granule_size_mask = max_granule_size - 1;
unsigned int max_granule_mask = max_granule - 1U;
/* Base must be aligned to the max granularity */
assert((ARM_SP_IMAGE_NS_BUF_BASE & max_granule_size_mask) == 0);
assert((ARM_SP_IMAGE_NS_BUF_BASE & max_granule_mask) == 0);
/* Size must be a multiple of the max granularity */
assert((ARM_SP_IMAGE_NS_BUF_SIZE & max_granule_size_mask) == 0);
assert((ARM_SP_IMAGE_NS_BUF_SIZE & max_granule_mask) == 0);
#endif /* ENABLE_ASSERTIONS */