Clarify platform porting interface to TSP
* Move TSP platform porting functions to new file:
include/bl32/tsp/platform_tsp.h.
* Create new TSP_IRQ_SEC_PHY_TIMER definition for use by the generic
TSP interrupt handling code, instead of depending on the FVP
specific definition IRQ_SEC_PHY_TIMER.
* Rename TSP platform porting functions from bl32_* to tsp_*, and
definitions from BL32_* to TSP_*.
* Update generic TSP code to use new platform porting function names
and definitions.
* Update FVP port accordingly and move all TSP source files to:
plat/fvp/tsp/.
* Update porting guide with above changes.
Note: THIS CHANGE REQUIRES ALL PLATFORM PORTS OF THE TSP TO
BE UPDATED
Fixes ARM-software/tf-issues#167
Change-Id: Ic0ff8caf72aebb378d378193d2f017599fc6b78f
This commit is contained in:
Dan Handley
parent
da0af78aa2
commit
5a06bb7e0b
2
Makefile
2
Makefile
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@ -174,8 +174,6 @@ endif
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INCLUDES += -Iinclude/bl31 \
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-Iinclude/bl31/services \
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-Iinclude/bl32 \
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-Iinclude/bl32/payloads \
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-Iinclude/common \
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-Iinclude/drivers \
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-Iinclude/drivers/arm \
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@ -120,8 +120,8 @@ func tsp_entrypoint
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* specific early arch. setup e.g. mmu setup
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* ---------------------------------------------
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*/
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bl bl32_early_platform_setup
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bl bl32_plat_arch_setup
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bl tsp_early_platform_setup
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bl tsp_plat_arch_setup
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/* ---------------------------------------------
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* Jump to main function.
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@ -68,8 +68,8 @@ SECTIONS
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__DATA_END__ = .;
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} >RAM
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#ifdef BL32_PROGBITS_LIMIT
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ASSERT(. <= BL32_PROGBITS_LIMIT, "BL3-2 progbits has exceeded its limit.")
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#ifdef TSP_PROGBITS_LIMIT
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ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
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#endif
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stacks (NOLOAD) : {
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@ -28,6 +28,8 @@
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# POSSIBILITY OF SUCH DAMAGE.
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#
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INCLUDES += -Iinclude/bl32/tsp
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BL32_SOURCES += bl32/tsp/tsp_main.c \
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bl32/tsp/aarch64/tsp_entrypoint.S \
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bl32/tsp/aarch64/tsp_exceptions.S \
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@ -50,7 +52,7 @@ $(eval $(call add_define,TSP_INIT_ASYNC))
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# Include the platform-specific TSP Makefile
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# If no platform-specific TSP Makefile exists, it means TSP is not supported
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# on this platform.
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TSP_PLAT_MAKEFILE := bl32/tsp/tsp-${PLAT}.mk
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TSP_PLAT_MAKEFILE := plat/${PLAT}/tsp/tsp-${PLAT}.mk
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ifeq (,$(wildcard ${TSP_PLAT_MAKEFILE}))
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$(error TSP is not supported on platform ${PLAT})
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else
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@ -88,7 +88,7 @@ int32_t tsp_fiq_handler(void)
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id = plat_ic_get_pending_interrupt_id();
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/* TSP can only handle the secure physical timer interrupt */
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if (id != IRQ_SEC_PHY_TIMER)
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if (id != TSP_IRQ_SEC_PHY_TIMER)
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return TSP_EL3_FIQ;
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/*
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@ -96,7 +96,7 @@ int32_t tsp_fiq_handler(void)
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* another secure interrupt through an assertion.
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*/
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id = plat_ic_acknowledge_interrupt();
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assert(id == IRQ_SEC_PHY_TIMER);
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assert(id == TSP_IRQ_SEC_PHY_TIMER);
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tsp_generic_timer_handler();
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plat_ic_end_of_interrupt(id);
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@ -33,6 +33,7 @@
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#include <debug.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <platform_tsp.h>
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#include <spinlock.h>
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#include <tsp.h>
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#include "tsp_private.h"
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@ -116,7 +117,7 @@ uint64_t tsp_main(void)
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uint32_t linear_id = platform_get_core_pos(mpidr);
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/* Initialize the platform */
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bl32_platform_setup();
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tsp_platform_setup();
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/* Initialize secure/applications state here */
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tsp_generic_timer_start();
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@ -193,30 +193,42 @@ file is found in [plat/fvp/include/platform_def.h].
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Defines the base address in non-secure DRAM where BL2 loads the BL3-3 binary
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image. Must be aligned on a page-size boundary.
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If the BL3-2 image is supported by the platform, the following constants must
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be defined as well:
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If a BL3-2 image is supported by the platform, the following constants must
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also be defined:
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* **#define : TSP_SEC_MEM_BASE**
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* **#define : BL32_IMAGE_NAME**
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Defines the base address of the secure memory used by the BL3-2 image on the
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platform.
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* **#define : TSP_SEC_MEM_SIZE**
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Defines the size of the secure memory used by the BL3-2 image on the
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platform.
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Name of the BL3-2 binary image on the host file-system. This name is used by
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BL2 to load BL3-2 into secure memory from platform storage.
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* **#define : BL32_BASE**
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Defines the base address in secure memory where BL2 loads the BL3-2 binary
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image. Must be inside the secure memory identified by `TSP_SEC_MEM_BASE` and
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`TSP_SEC_MEM_SIZE` constants. Must also be aligned on a page-size boundary.
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image. Must be aligned on a page-size boundary.
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* **#define : BL32_LIMIT**
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Defines the maximum address that the BL3-2 image can occupy. Must be inside
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the secure memory identified by `TSP_SEC_MEM_BASE` and `TSP_SEC_MEM_SIZE`
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constants.
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Defines the maximum address that the BL3-2 image can occupy.
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If the Test Secure-EL1 Payload (TSP) instantiation of BL3-2 is supported by the
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platform, the following constants must also be defined:
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* **#define : TSP_SEC_MEM_BASE**
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Defines the base address of the secure memory used by the TSP image on the
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platform. This must be at the same address or below `BL32_BASE`.
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* **#define : TSP_SEC_MEM_SIZE**
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Defines the size of the secure memory used by the BL3-2 image on the
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platform. `TSP_SEC_MEM_BASE` and `TSP_SEC_MEM_SIZE` must fully accomodate
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the memory required by the BL3-2 image, defined by `BL32_BASE` and
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`BL32_LIMIT`.
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* **#define : TSP_IRQ_SEC_PHY_TIMER**
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Defines the ID of the secure physical generic timer interrupt used by the
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TSP's interrupt handling code.
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If the platform port uses the IO storage framework, the following constants
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must also be defined:
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@ -241,7 +253,7 @@ memory layout implies some image overlaying like on FVP.
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Defines the maximum address in secure RAM that the BL3-1's progbits sections
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can occupy.
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* **#define : BL32_PROGBITS_LIMIT**
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* **#define : TSP_PROGBITS_LIMIT**
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Defines the maximum address that the TSP's progbits sections can occupy.
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@ -0,0 +1,44 @@
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/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_TSP_H__
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/*******************************************************************************
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* Mandatory TSP functions (only if platform contains a TSP)
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******************************************************************************/
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void tsp_early_platform_setup(void);
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void tsp_plat_arch_setup(void);
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void tsp_platform_setup(void);
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#define __PLATFORM_H__
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#endif
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@ -78,6 +78,7 @@ int plat_crash_console_putc(int c);
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/*******************************************************************************
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* Mandatory BL1 functions
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******************************************************************************/
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void bl1_early_platform_setup(void);
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void bl1_plat_arch_setup(void);
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void bl1_platform_setup(void);
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struct meminfo *bl1_plat_sec_mem_layout(void);
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@ -98,6 +99,7 @@ void bl1_init_bl2_mem_layout(const struct meminfo *bl1_mem_layout,
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/*******************************************************************************
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* Mandatory BL2 functions
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******************************************************************************/
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void bl2_early_platform_setup(struct meminfo *mem_layout);
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void bl2_plat_arch_setup(void);
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void bl2_platform_setup(void);
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struct meminfo *bl2_plat_sec_mem_layout(void);
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@ -184,11 +186,6 @@ unsigned int plat_get_aff_state(unsigned int, unsigned long);
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******************************************************************************/
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void bl31_plat_enable_mmu(uint32_t flags);
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/*******************************************************************************
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* Mandatory BL3-2 functions (only if platform contains a BL3-2)
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******************************************************************************/
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void bl32_platform_setup(void);
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/*******************************************************************************
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* Optional BL3-2 functions (may be overridden)
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******************************************************************************/
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@ -32,9 +32,9 @@
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <gic_v2.h>
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#include <platform_def.h>
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#include <pl011.h>
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#include "../drivers/pwrc/fvp_pwrc.h"
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#include "platform_def.h"
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.globl platform_get_entrypoint
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.globl plat_secondary_cold_boot_setup
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@ -32,7 +32,7 @@
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include <../fvp_def.h>
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#include "../fvp_def.h"
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/*******************************************************************************
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@ -131,8 +131,8 @@
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#if FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_SRAM
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# define TSP_SEC_MEM_BASE FVP_TRUSTED_SRAM_BASE
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# define TSP_SEC_MEM_SIZE FVP_TRUSTED_SRAM_SIZE
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# define TSP_PROGBITS_LIMIT BL2_BASE
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# define BL32_BASE FVP_TRUSTED_SRAM_BASE
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# define BL32_PROGBITS_LIMIT BL2_BASE
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# define BL32_LIMIT BL31_BASE
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#elif FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM
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# define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE
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@ -144,6 +144,11 @@
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# error "Unsupported FVP_TSP_RAM_LOCATION_ID value"
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#endif
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/*
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* ID of the secure physical generic timer interrupt used by the TSP.
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*/
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#define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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@ -151,11 +156,6 @@
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#define MAX_XLAT_TABLES 2
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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* ID of the secure physical generic timer interrupt.
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******************************************************************************/
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#define IRQ_SEC_PHY_TIMER 29
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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@ -35,4 +35,4 @@ BL32_SOURCES += drivers/arm/gic/arm_gic.c \
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plat/common/plat_gic.c \
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plat/fvp/aarch64/fvp_common.c \
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plat/fvp/aarch64/fvp_helpers.S \
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plat/fvp/bl32_fvp_setup.c
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plat/fvp/tsp/tsp_fvp_setup.c
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@ -30,9 +30,9 @@
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#include <bl_common.h>
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#include <console.h>
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#include <platform.h>
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#include "fvp_def.h"
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#include "fvp_private.h"
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#include <platform_tsp.h>
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#include "../fvp_def.h"
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#include "../fvp_private.h"
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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@ -66,7 +66,7 @@ extern unsigned long __COHERENT_RAM_END__;
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/*******************************************************************************
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* Initialize the UART
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******************************************************************************/
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void bl32_early_platform_setup(void)
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void tsp_early_platform_setup(void)
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{
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/*
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* Initialize a different console than already in use to display
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@ -81,7 +81,7 @@ void bl32_early_platform_setup(void)
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/*******************************************************************************
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* Perform platform specific setup placeholder
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******************************************************************************/
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void bl32_platform_setup(void)
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void tsp_platform_setup(void)
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{
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fvp_gic_init();
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}
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@ -90,7 +90,7 @@ void bl32_platform_setup(void)
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only intializes the MMU
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******************************************************************************/
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void bl32_plat_arch_setup(void)
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void tsp_plat_arch_setup(void)
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{
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fvp_configure_mmu_el1(BL32_RO_BASE,
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(BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
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@ -29,7 +29,7 @@
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#
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TSPD_DIR := services/spd/tspd
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SPD_INCLUDES := -Iinclude/bl32/payloads
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SPD_INCLUDES := -Iinclude/bl32/tsp
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SPD_SOURCES := services/spd/tspd/tspd_common.c \
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services/spd/tspd/tspd_helpers.S \
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