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rockchip: rk3399: Fix CAS latency setting 

The F1 CAS latency setting was not bit shifted, which resulted in
setting the DRAM additive latency value instead.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
This commit is contained in:
Derek Basehore 2017-02-09 22:02:42 -08:00 committed by Xing Zheng
parent 43f52e92e4
commit 5a5dc61713
1 changed files with 1 additions and 1 deletions
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2
plat/rockchip/rk3399/drivers/dram/dfs.c
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@ -1254,7 +1254,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY);
/* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */
mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8,
pdram_timing->cl * 2);
(pdram_timing->cl * 2) << 8);
/* PI_47 PI_TREF_F1:RW:16:16 */
mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16,
pdram_timing->trefi << 16);