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fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif 

A RAS error may be triggered while offline core in OS. Error:
Uncorrected software error in the Distributor, with IERR=9,SERR=f.
Core put to sleep before its Group enables were cleared.

gicv3_cpuif_disable() will be called in offline core flow.
According to GIC architecture version 3 and version 4:
Architectural execution of a DSB instruction guarantees that
the last value written to ICC_IGRPEN0_EL1, ICC_IGRPEN1_EL1,
ICC_IGRPEN1_EL3 or GICC_CTLR.{EnableGrp0, EnableGrp1}is observed
by the associated Redistributor.
An ISB or other context synchronization operation must precede
the DSB to ensure visibility of System register writes.

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: Iff1475657f401374c761b5e8f2f5b3a4b2040e9d
This commit is contained in:
Ming Huang 2021-06-04 16:23:22 +08:00
parent c791113776
commit 5a5e0aac39
1 changed files with 4 additions and 0 deletions
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4
drivers/arm/gic/v3/gicv3_main.c
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@ -332,6 +332,8 @@ void gicv3_cpuif_enable(unsigned int proc_num)
write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
IGRPEN1_EL3_ENABLE_G1S_BIT);
isb();
/* Add DSB to ensure visibility of System register writes */
dsb();
}
/*******************************************************************************
@ -363,6 +365,8 @@ void gicv3_cpuif_disable(unsigned int proc_num)
/* Synchronise accesses to group enable registers */
isb();
/* Add DSB to ensure visibility of System register writes */
dsb();
/* Mark the connected core as asleep */
gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];