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Unify type of "cpu_idx" across PSCI module. 

NOTE for platform integrators:
   API `plat_psci_stat_get_residency()` third argument
   `last_cpu_idx` is changed from "signed int" to the
   "unsigned int" type.

Issue / Trouble points
1. cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places leading to coverity issues.

2. Underlying platform API's return cpu_idx as `unsigned int`
and comparison is performed with platform specific defines
`PLAFORM_xxx` which is not consistent

Misra Rule 10.4:
The value of a complex expression of integer type may only be cast to
a type that is narrower and of the same signedness as the underlying
type of the expression.

Based on above points, cpu_idx is kept as `unsigned int` to match
the API's and low-level functions and platform defines are updated
where ever required

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
This commit is contained in:
Deepika Bhavnani 2019-12-13 10:23:18 -06:00
parent 22d12c4148
commit 5b33ad174a
25 changed files with 99 additions and 90 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
docs/getting_started/porting-guide.rst
View File

@ -1999,7 +1999,7 @@ Function : plat_psci_stat_get_residency() [optional]
::
Argument : unsigned int, const psci_power_state_t *, int
Argument : unsigned int, const psci_power_state_t *, unsigned int
Return : u_register_t
This is an optional interface that is is invoked after resuming from a low power

5
drivers/arm/css/scp/css_pm_scmi.c
View File

@ -186,7 +186,7 @@ void css_scp_off(const struct psci_power_state *target_state)
void css_scp_on(u_register_t mpidr)
{
unsigned int lvl = 0;
int ret, core_pos;
int core_pos, ret;
uint32_t scmi_pwr_state = 0;
for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
@ -196,7 +196,8 @@ void css_scp_on(u_register_t mpidr)
SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
core_pos = plat_core_pos_by_mpidr(mpidr);
assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
assert((core_pos >= 0) &&
(((unsigned int)core_pos) < PLATFORM_CORE_COUNT));
ret = scmi_pwr_state_set(scmi_handle,
plat_css_core_pos_to_scmi_dmn_id_map[core_pos],

4
include/export/lib/utils_def_exp.h
View File

@ -25,11 +25,13 @@
# define L(_x) (_x)
# define LL(_x) (_x)
#else
# define U(_x) (_x##U)
# define U_(_x) (_x##U)
# define U(_x) U_(_x)
# define UL(_x) (_x##UL)
# define ULL(_x) (_x##ULL)
# define L(_x) (_x##L)
# define LL(_x) (_x##LL)
#endif
#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_LIB_UTILS_DEF_EXP_H */

2
include/lib/psci/psci.h
View File

@ -20,7 +20,7 @@
#ifdef PLAT_NUM_PWR_DOMAINS
#define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS
#else
#define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT)
#define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT)
#endif
#define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \

2
include/plat/arm/common/arm_def.h
View File

@ -21,7 +21,7 @@
/* Special value used to verify platform parameters from BL2 to BL31 */
#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
#define ARM_SYSTEM_COUNT 1
#define ARM_SYSTEM_COUNT U(1)
#define ARM_CACHE_WRITEBACK_SHIFT 6

2
include/plat/common/platform.h
View File

@ -237,7 +237,7 @@ void plat_psci_stat_accounting_start(const psci_power_state_t *state_info);
void plat_psci_stat_accounting_stop(const psci_power_state_t *state_info);
u_register_t plat_psci_stat_get_residency(unsigned int lvl,
const psci_power_state_t *state_info,
int last_cpu_idx);
unsigned int last_cpu_idx);
plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
const plat_local_state_t *states,
unsigned int ncpu);

13
lib/psci/psci_main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -219,16 +219,19 @@ int psci_cpu_off(void)
int psci_affinity_info(u_register_t target_affinity,
unsigned int lowest_affinity_level)
{
int target_idx;
int ret;
unsigned int target_idx;
/* We dont support level higher than PSCI_CPU_PWR_LVL */
if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
return PSCI_E_INVALID_PARAMS;
/* Calculate the cpu index of the target */
target_idx = plat_core_pos_by_mpidr(target_affinity);
if (target_idx == -1)
ret = plat_core_pos_by_mpidr(target_affinity);
if (ret == -1) {
return PSCI_E_INVALID_PARAMS;
}
target_idx = (unsigned int)ret;
/*
* Generic management:
@ -245,7 +248,7 @@ int psci_affinity_info(u_register_t target_affinity,
* target CPUs shutdown was not seen by the current CPU's cluster. And
* so the cache may contain stale data for the target CPU.
*/
flush_cpu_data_by_index((unsigned int)target_idx,
flush_cpu_data_by_index(target_idx,
psci_svc_cpu_data.aff_info_state);
return psci_get_aff_info_state_by_idx(target_idx);

4
lib/psci/psci_off.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -43,7 +43,7 @@ static void psci_set_power_off_state(psci_power_state_t *state_info)
int psci_do_cpu_off(unsigned int end_pwrlvl)
{
int rc = PSCI_E_SUCCESS;
int idx = (int) plat_my_core_pos();
unsigned int idx = plat_my_core_pos();
psci_power_state_t state_info;
unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};

24
lib/psci/psci_on.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -20,12 +20,12 @@
/*
* Helper functions for the CPU level spinlocks
*/
static inline void psci_spin_lock_cpu(int idx)
static inline void psci_spin_lock_cpu(unsigned int idx)
{
spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock);
}
static inline void psci_spin_unlock_cpu(int idx)
static inline void psci_spin_unlock_cpu(unsigned int idx)
{
spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock);
}
@ -61,12 +61,14 @@ int psci_cpu_on_start(u_register_t target_cpu,
{
int rc;
aff_info_state_t target_aff_state;
int target_idx = plat_core_pos_by_mpidr(target_cpu);
int ret = plat_core_pos_by_mpidr(target_cpu);
unsigned int target_idx = (unsigned int)ret;
/* Calling function must supply valid input arguments */
assert(target_idx >= 0);
assert(ret >= 0);
assert(ep != NULL);
/*
* This function must only be called on platforms where the
* CPU_ON platform hooks have been implemented.
@ -93,7 +95,7 @@ int psci_cpu_on_start(u_register_t target_cpu,
* target CPUs shutdown was not seen by the current CPU's cluster. And
* so the cache may contain stale data for the target CPU.
*/
flush_cpu_data_by_index((unsigned int)target_idx,
flush_cpu_data_by_index(target_idx,
psci_svc_cpu_data.aff_info_state);
rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx));
if (rc != PSCI_E_SUCCESS)
@ -113,7 +115,7 @@ int psci_cpu_on_start(u_register_t target_cpu,
* turned OFF.
*/
psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
flush_cpu_data_by_index((unsigned int)target_idx,
flush_cpu_data_by_index(target_idx,
psci_svc_cpu_data.aff_info_state);
/*
@ -126,7 +128,7 @@ int psci_cpu_on_start(u_register_t target_cpu,
if (target_aff_state != AFF_STATE_ON_PENDING) {
assert(target_aff_state == AFF_STATE_OFF);
psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
flush_cpu_data_by_index((unsigned int)target_idx,
flush_cpu_data_by_index(target_idx,
psci_svc_cpu_data.aff_info_state);
assert(psci_get_aff_info_state_by_idx(target_idx) ==
@ -146,11 +148,11 @@ int psci_cpu_on_start(u_register_t target_cpu,
if (rc == PSCI_E_SUCCESS)
/* Store the re-entry information for the non-secure world. */
cm_init_context_by_index((unsigned int)target_idx, ep);
cm_init_context_by_index(target_idx, ep);
else {
/* Restore the state on error. */
psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF);
flush_cpu_data_by_index((unsigned int)target_idx,
flush_cpu_data_by_index(target_idx,
psci_svc_cpu_data.aff_info_state);
}
@ -164,7 +166,7 @@ exit:
* are called by the common finisher routine in psci_common.c. The `state_info`
* is the psci_power_state from which this CPU has woken up from.
******************************************************************************/
void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info)
void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info)
{
/*
* Plat. management: Perform the platform specific actions

6
lib/psci/psci_private.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -301,7 +301,7 @@ void prepare_cpu_pwr_dwn(unsigned int power_level);
int psci_cpu_on_start(u_register_t target_cpu,
const entry_point_info_t *ep);
void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info);
void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info);
/* Private exported functions from psci_off.c */
int psci_do_cpu_off(unsigned int end_pwrlvl);
@ -312,7 +312,7 @@ void psci_cpu_suspend_start(const entry_point_info_t *ep,
psci_power_state_t *state_info,
unsigned int is_power_down_state);
void psci_cpu_suspend_finish(int cpu_idx, const psci_power_state_t *state_info);
void psci_cpu_suspend_finish(unsigned int cpu_idx, const psci_power_state_t *state_info);
/* Private exported functions from psci_helpers.S */
void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level);

16
lib/psci/psci_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -91,9 +91,9 @@ static void __init psci_update_pwrlvl_limits(void)
for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
psci_get_parent_pwr_domain_nodes(cpu_idx,
(unsigned int)PLAT_MAX_PWR_LVL,
PLAT_MAX_PWR_LVL,
temp_index);
for (j = (int) PLAT_MAX_PWR_LVL - 1; j >= 0; j--) {
for (j = (int)PLAT_MAX_PWR_LVL - 1; j >= 0; j--) {
if (temp_index[j] != nodes_idx[j]) {
nodes_idx[j] = temp_index[j];
psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx
@ -115,8 +115,8 @@ static unsigned int __init populate_power_domain_tree(const unsigned char
{
unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl;
unsigned int node_index = 0U, num_children;
int parent_node_index = 0;
int level = (int) PLAT_MAX_PWR_LVL;
unsigned int parent_node_index = 0U;
int level = (int)PLAT_MAX_PWR_LVL;
/*
* For each level the inputs are:
@ -145,8 +145,8 @@ static unsigned int __init populate_power_domain_tree(const unsigned char
for (j = node_index;
j < (node_index + num_children); j++)
psci_init_pwr_domain_node((unsigned char)j,
parent_node_index - 1,
(unsigned char)level);
parent_node_index - 1U,
(unsigned char)level);
node_index = j;
num_nodes_at_next_lvl += num_children;
@ -162,7 +162,7 @@ static unsigned int __init populate_power_domain_tree(const unsigned char
}
/* Validate the sanity of array exported by the platform */
assert(j <= (unsigned int)PLATFORM_CORE_COUNT);
assert(j <= PLATFORM_CORE_COUNT);
return j;
}

12
lib/psci/psci_stat.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -28,7 +28,7 @@ typedef struct psci_stat {
* that goes to power down in non cpu power domains.
*/
static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {
[0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS - 1] = -1};
[0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS - 1U] = -1};
/*
* Following are used to store PSCI STAT values for
@ -77,7 +77,7 @@ void psci_stats_update_pwr_down(unsigned int end_pwrlvl,
const psci_power_state_t *state_info)
{
unsigned int lvl, parent_idx;
int cpu_idx = (int) plat_my_core_pos();
unsigned int cpu_idx = plat_my_core_pos();
assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
assert(state_info != NULL);
@ -94,7 +94,7 @@ void psci_stats_update_pwr_down(unsigned int end_pwrlvl,
* The power domain is entering a low power state, so this is
* the last CPU for this power domain
*/
last_cpu_in_non_cpu_pd[parent_idx] = cpu_idx;
last_cpu_in_non_cpu_pd[parent_idx] = (int)cpu_idx;
parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
}
@ -110,7 +110,7 @@ void psci_stats_update_pwr_up(unsigned int end_pwrlvl,
const psci_power_state_t *state_info)
{
unsigned int lvl, parent_idx;
int cpu_idx = (int) plat_my_core_pos();
unsigned int cpu_idx = plat_my_core_pos();
int stat_idx;
plat_local_state_t local_state;
u_register_t residency;
@ -150,7 +150,7 @@ void psci_stats_update_pwr_up(unsigned int end_pwrlvl,
/* Call into platform interface to calculate residency. */
residency = plat_psci_stat_get_residency(lvl, state_info,
last_cpu_in_non_cpu_pd[parent_idx]);
(unsigned int)last_cpu_in_non_cpu_pd[parent_idx]);
/* Initialize back to reset value */
last_cpu_in_non_cpu_pd[parent_idx] = -1;

8
lib/psci/psci_suspend.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -25,7 +25,7 @@
* This function does generic and platform specific operations after a wake-up
* from standby/retention states at multiple power levels.
******************************************************************************/
static void psci_suspend_to_standby_finisher(int cpu_idx,
static void psci_suspend_to_standby_finisher(unsigned int cpu_idx,
unsigned int end_pwrlvl)
{
unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
@ -157,7 +157,7 @@ void psci_cpu_suspend_start(const entry_point_info_t *ep,
unsigned int is_power_down_state)
{
int skip_wfi = 0;
int idx = (int) plat_my_core_pos();
unsigned int idx = plat_my_core_pos();
unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
/*
@ -276,7 +276,7 @@ exit:
* are called by the common finisher routine in psci_common.c. The `state_info`
* is the psci_power_state from which this CPU has woken up from.
******************************************************************************/
void psci_cpu_suspend_finish(int cpu_idx, const psci_power_state_t *state_info)
void psci_cpu_suspend_finish(unsigned int cpu_idx, const psci_power_state_t *state_info)
{
unsigned int counter_freq;
unsigned int max_off_lvl;

10
plat/arm/board/a5ds/include/platform_def.h
View File

@ -89,15 +89,15 @@
#define A5DS_IRQ_SEC_SYS_TIMER 57
/* Default cluster count for A5DS */
#define A5DS_CLUSTER_COUNT 1
#define A5DS_CLUSTER_COUNT U(1)
/* Default number of CPUs per cluster on A5DS */
#define A5DS_MAX_CPUS_PER_CLUSTER 4
#define A5DS_MAX_CPUS_PER_CLUSTER U(4)
/* Default number of threads per CPU on A5DS */
#define A5DS_MAX_PE_PER_CPU 1
#define A5DS_MAX_PE_PER_CPU U(1)
#define A5DS_CORE_COUNT 4
#define A5DS_CORE_COUNT U(4)
#define A5DS_PRIMARY_CPU 0x0
@ -231,7 +231,7 @@
/* Required platform porting definitions */
#define PLATFORM_CORE_COUNT A5DS_CORE_COUNT
#define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT) + 1
PLATFORM_CORE_COUNT) + U(1)
#define PLAT_MAX_PWR_LVL 2

6
plat/arm/board/corstone700/include/platform_def.h
View File

@ -14,9 +14,9 @@
#include <plat/common/common_def.h>
/* Core/Cluster/Thread counts for Corstone700 */
#define CORSTONE700_CLUSTER_COUNT 1
#define CORSTONE700_MAX_CPUS_PER_CLUSTER 4
#define CORSTONE700_MAX_PE_PER_CPU 1
#define CORSTONE700_CLUSTER_COUNT U(1)
#define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4)
#define CORSTONE700_MAX_PE_PER_CPU U(1)
#define CORSTONE700_CORE_COUNT (CORSTONE700_CLUSTER_COUNT * \
CORSTONE700_MAX_CPUS_PER_CLUSTER * \
CORSTONE700_MAX_PE_PER_CPU)

11
plat/arm/board/fvp/include/platform_def.h
View File

@ -17,11 +17,12 @@
#include "../fvp_def.h"
/* Required platform porting definitions */
#define PLATFORM_CORE_COUNT \
(FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU)
#define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \
U(FVP_MAX_CPUS_PER_CLUSTER) * \
U(FVP_MAX_PE_PER_CPU))
#define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT) + 1
#define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \
PLATFORM_CORE_COUNT + U(1))
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
@ -32,7 +33,7 @@
/*
* Required ARM standard platform porting definitions
*/
#define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT
#define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT)
#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */

10
plat/arm/board/fvp_ve/fvp_ve_def.h
View File

@ -10,17 +10,17 @@
#include <lib/utils_def.h>
/* Default cluster count for FVP VE */
#define FVP_VE_CLUSTER_COUNT 1
#define FVP_VE_CLUSTER_COUNT U(1)
/* Default number of CPUs per cluster on FVP VE */
#define FVP_VE_MAX_CPUS_PER_CLUSTER 1
#define FVP_VE_MAX_CPUS_PER_CLUSTER U(1)
/* Default number of threads per CPU on FVP VE */
#define FVP_VE_MAX_PE_PER_CPU 1
#define FVP_VE_MAX_PE_PER_CPU U(1)
#define FVP_VE_CORE_COUNT 1
#define FVP_VE_CORE_COUNT U(1)
#define FVP_VE_PRIMARY_CPU 0x0
#define FVP_VE_PRIMARY_CPU 0x0
/*******************************************************************************
* FVP memory map related constants

6
plat/arm/board/fvp_ve/include/platform_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -211,9 +211,9 @@
#define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
/* Required platform porting definitions */
#define PLATFORM_CORE_COUNT 1
#define PLATFORM_CORE_COUNT FVP_VE_CLUSTER_COUNT
#define PLAT_NUM_PWR_DOMAINS ((FVP_VE_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT) + 1)
PLATFORM_CORE_COUNT) + U(1))
#define PLAT_MAX_PWR_LVL 2

8
plat/arm/board/juno/juno_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -32,9 +32,9 @@
/*******************************************************************************
* Juno topology related constants
******************************************************************************/
#define JUNO_CLUSTER_COUNT 2
#define JUNO_CLUSTER0_CORE_COUNT 2
#define JUNO_CLUSTER1_CORE_COUNT 4
#define JUNO_CLUSTER_COUNT U(2)
#define JUNO_CLUSTER0_CORE_COUNT U(2)
#define JUNO_CLUSTER1_CORE_COUNT U(4)
/*******************************************************************************
* TZC-400 related constants

6
plat/arm/board/rde1edge/include/platform_def.h
View File

@ -11,9 +11,9 @@
#include <sgi_base_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT 2
#define CSS_SGI_MAX_CPUS_PER_CLUSTER 8
#define CSS_SGI_MAX_PE_PER_CPU 2
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(8)
#define CSS_SGI_MAX_PE_PER_CPU U(2)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE

6
plat/arm/board/rdn1edge/include/platform_def.h
View File

@ -11,9 +11,9 @@
#include <sgi_base_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT 2
#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
#define CSS_SGI_MAX_PE_PER_CPU 1
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
#define CSS_SGI_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE

8
plat/arm/board/sgi575/include/platform_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -11,9 +11,9 @@
#include <sgi_base_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT 2
#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
#define CSS_SGI_MAX_PE_PER_CPU 1
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
#define CSS_SGI_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45000000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE

6
plat/arm/board/sgm775/include/platform_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,8 +9,8 @@
#include <sgm_base_platform_def.h>
#define PLAT_MAX_CPUS_PER_CLUSTER 8
#define PLAT_MAX_PE_PER_CPU 1
#define PLAT_MAX_CPUS_PER_CLUSTER U(8)
#define PLAT_MAX_PE_PER_CPU U(1)
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes

6
plat/arm/css/sgm/include/sgm_base_platform_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,8 +17,8 @@
#include <plat/common/common_def.h>
/* CPU topology */
#define PLAT_ARM_CLUSTER_COUNT 1
#define PLAT_ARM_CLUSTER_CORE_COUNT 8
#define PLAT_ARM_CLUSTER_COUNT U(1)
#define PLAT_ARM_CLUSTER_CORE_COUNT U(8)
#define PLATFORM_CORE_COUNT PLAT_ARM_CLUSTER_CORE_COUNT
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2

6
plat/common/plat_psci_common.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -92,7 +92,7 @@ void plat_psci_stat_accounting_stop(
*/
u_register_t plat_psci_stat_get_residency(unsigned int lvl,
const psci_power_state_t *state_info,
int last_cpu_idx)
unsigned int last_cpu_idx)
{
plat_local_state_t state;
unsigned long long pwrup_ts = 0, pwrdn_ts = 0;
@ -103,7 +103,7 @@ u_register_t plat_psci_stat_get_residency(unsigned int lvl,
assert(last_cpu_idx <= PLATFORM_CORE_COUNT);
if (lvl == PSCI_CPU_PWR_LVL)
assert((unsigned int)last_cpu_idx == plat_my_core_pos());
assert(last_cpu_idx == plat_my_core_pos());
/*
* If power down is requested, then timestamp capture will