Merge pull request #247 from achingupta/ag/tf-issues#275
Call reset handlers upon BL3-1 entry.
This commit is contained in:
commit
5b36ab3e0b
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@ -61,15 +61,21 @@ func bl31_entrypoint
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bic x0, x0, #SCTLR_EE_BIT
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msr sctlr_el3, x0
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isb
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#endif
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/* -----------------------------------------------------
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* Perform any processor specific actions upon reset
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* e.g. cache, tlb invalidations etc. Override the
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* Boot ROM(BL0) programming sequence
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* -----------------------------------------------------
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/* ---------------------------------------------
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* When RESET_TO_BL31 is true, perform any
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* processor specific actions upon reset e.g.
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* cache, tlb invalidations, errata workarounds
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* etc.
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* When RESET_TO_BL31 is false, perform any
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* processor specific actions which undo or are
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* in addition to the actions performed by the
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* reset handler in the Boot ROM (BL1).
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* ---------------------------------------------
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*/
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bl reset_handler
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#endif
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/* ---------------------------------------------
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* Enable the instruction cache, stack pointer
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* and data access alignment checks
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@ -9,12 +9,13 @@ Contents :
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4. [Power State Coordination Interface](#4--power-state-coordination-interface)
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5. [Secure-EL1 Payloads and Dispatchers](#5--secure-el1-payloads-and-dispatchers)
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6. [Crash Reporting in BL3-1](#6--crash-reporting-in-bl3-1)
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7. [CPU specific operations framework](#7--cpu-specific-operations-framework)
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8. [Memory layout of BL images](#8-memory-layout-of-bl-images)
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9. [Firmware Image Package (FIP)](#9--firmware-image-package-fip)
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10. [Use of coherent memory in Trusted Firmware](#10--use-of-coherent-memory-in-trusted-firmware)
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11. [Code Structure](#11--code-structure)
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12. [References](#12--references)
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7. [Guidelines for Reset Handlers](#7--guidelines-for-reset-handlers)
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8. [CPU specific operations framework](#8--cpu-specific-operations-framework)
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9. [Memory layout of BL images](#9-memory-layout-of-bl-images)
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10. [Firmware Image Package (FIP)](#10--firmware-image-package-fip)
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11. [Use of coherent memory in Trusted Firmware](#11--use-of-coherent-memory-in-trusted-firmware)
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12. [Code Structure](#12--code-structure)
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13. [References](#13--references)
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1. Introduction
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@ -960,8 +961,48 @@ The sample crash output is shown below.
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fpexc32_el2 :0x0000000004000700
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sp_el0 :0x0000000004010780
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7. Guidelines for Reset Handlers
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---------------------------------
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7. CPU specific operations framework
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Trusted Firmware implements a framework that allows CPU and platform ports to
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perform actions immediately after a CPU is released from reset in both the cold
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and warm boot paths. This is done by calling the `reset_handler()` function in
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both the BL1 and BL3-1 images. It in turn calls the platform and CPU specific
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reset handling functions.
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Details for implementing a CPU specific reset handler can be found in
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Section 8. Details for implementing a platform specific reset handler can be
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found in the [Porting Guide](see the `plat_reset_handler()` function).
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When adding functionality to a reset handler, the following points should be
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kept in mind.
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1. The first reset handler in the system exists either in a ROM image
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(e.g. BL1), or BL3-1 if `RESET_TO_BL31` is true. This may be detected at
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compile time using the constant `FIRST_RESET_HANDLER_CALL`.
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2. When considering ROM images, it's important to consider non TF-based ROMs
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and ROMs based on previous versions of the TF code.
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3. If the functionality should be applied to a ROM and there is no possibility
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of a ROM being used that does not apply the functionality (or equivalent),
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then the functionality should be applied within a `#if
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FIRST_RESET_HANDLER_CALL` block.
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4. If the functionality should execute in BL3-1 in order to override or
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supplement a ROM version of the functionality, then the functionality
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should be applied in the `#else` part of a `#if FIRST_RESET_HANDLER_CALL`
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block.
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5. If the functionality should be applied to a ROM but there is a possibility
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of ROMs being used that do not apply the functionality, then the
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functionality should be applied outside of a `FIRST_RESET_HANDLER_CALL`
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block, so that BL3-1 has an opportunity to apply the functionality instead.
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In this case, additional code may be needed to cope with different ROMs
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that do or do not apply the functionality.
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8. CPU specific operations framework
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-----------------------------
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Certain aspects of the ARMv8 architecture are implementation defined,
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@ -1026,6 +1067,9 @@ in midr are used to find the matching `cpu_ops` entry. The `reset_func()` in
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the returned `cpu_ops` is then invoked which executes the required reset
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handling for that CPU and also any errata workarounds enabled by the platform.
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Refer to Section "Guidelines for Reset Handlers" for general guidelines
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regarding placement of code in a reset handler.
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### CPU specific power down sequence
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During the BL3-1 initialization sequence, the pointer to the matching `cpu_ops`
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@ -1056,7 +1100,7 @@ be reported and a pointer to the ASCII list of register names in a format
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expected by the crash reporting framework.
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8. Memory layout of BL images
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9. Memory layout of BL images
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-----------------------------
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Each bootloader image can be divided in 2 parts:
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@ -1378,7 +1422,7 @@ Loading the BL3-2 image in DRAM doesn't change the memory layout of the other
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images in Trusted SRAM.
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9. Firmware Image Package (FIP)
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10. Firmware Image Package (FIP)
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---------------------------------
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Using a Firmware Image Package (FIP) allows for packing bootloader images (and
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@ -1456,7 +1500,7 @@ Currently the FVP's policy only allows loading of a known set of images. The
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platform policy can be modified to allow additional images.
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10. Use of coherent memory in Trusted Firmware
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11. Use of coherent memory in Trusted Firmware
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----------------------------------------------
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There might be loss of coherency when physical memory with mismatched
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@ -1657,7 +1701,7 @@ reserve memory in `cpu_data` by defining the macro `PLAT_PCPU_DATA_SIZE` (see
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the [Porting Guide]). Refer to the reference platform code for examples.
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11. Code Structure
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12. Code Structure
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-------------------
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Trusted Firmware code is logically divided between the three boot loader
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@ -1702,7 +1746,7 @@ FDTs provide a description of the hardware platform and are used by the Linux
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kernel at boot time. These can be found in the `fdts` directory.
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12. References
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13. References
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---------------
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1. Trusted Board Boot Requirements CLIENT PDD (ARM DEN 0006B-5). Available
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@ -483,7 +483,9 @@ specific errata workarounds could also be implemented here. The api should
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preserve the value in x10 register as it is used by the caller to store the
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return address.
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The default implementation doesn't do anything.
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The default implementation doesn't do anything. If a platform needs to override
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the default implementation, refer to the [Firmware Design Guide] for general
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guidelines regarding placement of code in a reset handler.
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### Function : plat_disable_acp()
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@ -1476,6 +1478,7 @@ _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._
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[IMF Design Guide]: interrupt-framework-design.md
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[User Guide]: user-guide.md
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[FreeBSD]: http://www.freebsd.org
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[Firmware Design Guide]: firmware-design.md
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[plat/common/aarch64/platform_mp_stack.S]: ../plat/common/aarch64/platform_mp_stack.S
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[plat/common/aarch64/platform_up_stack.S]: ../plat/common/aarch64/platform_up_stack.S
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@ -90,6 +90,18 @@
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(_p)->h.attr = (uint32_t)(_attr) ; \
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} while (0)
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/*******************************************************************************
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* Constant that indicates if this is the first version of the reset handler
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* contained in an image. This will be the case when the image is BL1 or when
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* its BL3-1 and RESET_TO_BL31 is true. This constant enables a subsequent
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* version of the reset handler to perform actions that override the ones
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* performed in the first version of the code. This will be required when the
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* first version exists in an un-modifiable image e.g. a BootROM image.
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******************************************************************************/
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#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
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#define FIRST_RESET_HANDLER_CALL
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#endif
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#ifndef __ASSEMBLY__
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#include <cdefs.h> /* For __dead2 */
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#include <cassert.h>
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@ -40,7 +40,7 @@
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CPU_MIDR: /* cpu_ops midr */
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.space 8
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/* Reset fn is needed in BL at reset vector */
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#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
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#if IMAGE_BL1 || IMAGE_BL31
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CPU_RESET_FUNC: /* cpu_ops reset_func */
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.space 8
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#endif
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@ -65,7 +65,7 @@ CPU_OPS_SIZE = .
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.section cpu_ops, "a"; .align 3
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.type cpu_ops_\_name, %object
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.quad \_midr
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#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
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#if IMAGE_BL1 || IMAGE_BL31
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.if \_noresetfunc
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.quad 0
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.else
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@ -29,6 +29,7 @@
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <cortex_a53.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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@ -58,13 +59,17 @@ func cortex_a53_disable_smp
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func cortex_a53_reset_func
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/* ---------------------------------------------
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* As a bare minimum enable the SMP bit.
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* As a bare minimum enable the SMP bit if it is
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* not already set.
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* ---------------------------------------------
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*/
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mrs x0, CPUECTLR_EL1
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tst x0, #CPUECTLR_SMP_BIT
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b.ne skip_smp_setup
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orr x0, x0, #CPUECTLR_SMP_BIT
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msr CPUECTLR_EL1, x0
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isb
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skip_smp_setup:
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ret
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func cortex_a53_core_pwr_dwn
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@ -30,6 +30,7 @@
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <bl_common.h>
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#include <cortex_a57.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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@ -99,9 +100,17 @@ func errata_a57_806969_wa
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ret
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#endif
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apply_806969:
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/*
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* Test if errata has already been applied in an earlier
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* invocation of the reset handler and does not need to
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* be applied again.
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*/
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mrs x1, CPUACTLR_EL1
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tst x1, #CPUACTLR_NO_ALLOC_WBWA
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b.ne skip_806969
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orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA
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msr CPUACTLR_EL1, x1
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skip_806969:
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ret
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@ -123,9 +132,17 @@ func errata_a57_813420_wa
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ret
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#endif
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apply_813420:
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/*
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* Test if errata has already been applied in an earlier
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* invocation of the reset handler and does not need to
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* be applied again.
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*/
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mrs x1, CPUACTLR_EL1
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tst x1, #CPUACTLR_DCC_AS_DCCI
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b.ne skip_813420
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orr x1, x1, #CPUACTLR_DCC_AS_DCCI
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msr CPUACTLR_EL1, x1
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skip_813420:
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ret
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/* -------------------------------------------------
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@ -154,13 +171,18 @@ func cortex_a57_reset_func
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mov x0, x20
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bl errata_a57_813420_wa
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#endif
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/* ---------------------------------------------
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* As a bare minimum enable the SMP bit.
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* As a bare minimum enable the SMP bit if it is
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* not already set.
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* ---------------------------------------------
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*/
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mrs x0, CPUECTLR_EL1
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tst x0, #CPUECTLR_SMP_BIT
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b.ne skip_smp_setup
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orr x0, x0, #CPUECTLR_SMP_BIT
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msr CPUECTLR_EL1, x0
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skip_smp_setup:
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isb
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ret x19
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@ -37,7 +37,7 @@
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#endif
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/* Reset fn is needed in BL at reset vector */
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#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
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#if IMAGE_BL1 || IMAGE_BL31
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/*
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* The reset handler common to all platforms. After a matching
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* cpu_ops structure entry is found, the correponding reset_handler
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@ -64,7 +64,7 @@ func reset_handler
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1:
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ret
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#endif /* IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31) */
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#endif /* IMAGE_BL1 || IMAGE_BL31 */
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#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
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/*
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@ -115,12 +115,20 @@ func platform_mem_init
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/* -----------------------------------------------------
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* void plat_reset_handler(void);
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*
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* Before adding code in this function, refer to the
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* guidelines in docs/firmware-design.md to determine
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* whether the code should reside within the
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* FIRST_RESET_HANDLER_CALL block or not.
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*
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* Implement workaround for defect id 831273 by enabling
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* an event stream every 65536 cycles and set the L2 RAM
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* latencies for Cortex-A57.
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* latencies for Cortex-A57. This code is included only
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* when FIRST_RESET_HANDLER_CALL is defined since it
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* should be executed only during BL1.
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* -----------------------------------------------------
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*/
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func plat_reset_handler
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#ifdef FIRST_RESET_HANDLER_CALL
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/* Read the MIDR_EL1 */
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mrs x0, midr_el1
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ubfx x1, x0, MIDR_PN_SHIFT, #12
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@ -135,11 +143,12 @@ func plat_reset_handler
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1:
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/* ---------------------------------------------
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* Enable the event stream every 65536 cycles
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* ---------------------------------------------
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*/
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* Enable the event stream every 65536 cycles
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* ---------------------------------------------
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*/
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mov x0, #(0xf << EVNTI_SHIFT)
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orr x0, x0, #EVNTEN_BIT
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msr CNTKCTL_EL1, x0
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isb
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#endif /* FIRST_RESET_HANDLER_CALL */
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ret
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@ -53,10 +53,19 @@ psci_aff_suspend_finish_entry:
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psci_aff_common_finish_entry:
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#if !RESET_TO_BL31
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/* ---------------------------------------------
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* Perform any processor specific actions which
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* undo or are in addition to the actions
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* performed by the reset handler in the BootROM
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* (BL1) e.g. cache, tlb invalidations, errata
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* workarounds etc.
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* ---------------------------------------------
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*/
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bl reset_handler
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/* ---------------------------------------------
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* Enable the instruction cache, stack pointer
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* and data access alignment checks. Also, set
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* the EL3 exception endianess to little-endian.
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* and data access alignment checks.
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* It can be assumed that BL3-1 entrypoint code
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* will do this when RESET_TO_BL31 is set. The
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* same assumption cannot be made when another
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