From 5bd1a177dd8e93d05cb97d0b68c44f3d90f8dae6 Mon Sep 17 00:00:00 2001 From: Anthony Zhou Date: Fri, 24 Feb 2017 14:44:21 +0800 Subject: [PATCH] Tegra: fiq_glue: fix MISRA defects Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Convert object type to match the type of function parameters [Rule 10.3] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses[Rule 20.7] Change-Id: I5cf83caafcc1650b545ca731bf3eb8f0bfeb362b Signed-off-by: Anthony Zhou --- plat/nvidia/tegra/common/tegra_fiq_glue.c | 69 ++++++++++++----------- 1 file changed, 35 insertions(+), 34 deletions(-) diff --git a/plat/nvidia/tegra/common/tegra_fiq_glue.c b/plat/nvidia/tegra/common/tegra_fiq_glue.c index c2bfb1c5d..2f4395872 100644 --- a/plat/nvidia/tegra/common/tegra_fiq_glue.c +++ b/plat/nvidia/tegra/common/tegra_fiq_glue.c @@ -18,13 +18,13 @@ #include #include -DEFINE_BAKERY_LOCK(tegra_fiq_lock); +static DEFINE_BAKERY_LOCK(tegra_fiq_lock); /******************************************************************************* * Static variables ******************************************************************************/ static uint64_t ns_fiq_handler_addr; -static unsigned int fiq_handler_active; +static uint32_t fiq_handler_active; static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT]; /******************************************************************************* @@ -37,7 +37,7 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id, { cpu_context_t *ctx = cm_get_context(NON_SECURE); el3_state_t *el3state_ctx = get_el3state_ctx(ctx); - int cpu = plat_my_core_pos(); + uint32_t cpu = plat_my_core_pos(); uint32_t irq; bakery_lock_get(&tegra_fiq_lock); @@ -52,22 +52,23 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id, * Save elr_el3 and spsr_el3 from the saved context, and overwrite * the context with the NS fiq_handler_addr and SPSR value. */ - fiq_state[cpu].elr_el3 = read_ctx_reg(el3state_ctx, CTX_ELR_EL3); - fiq_state[cpu].spsr_el3 = read_ctx_reg(el3state_ctx, CTX_SPSR_EL3); + fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); + fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); /* * Set the new ELR to continue execution in the NS world using the * FIQ handler registered earlier. */ assert(ns_fiq_handler_addr); - write_ctx_reg(el3state_ctx, CTX_ELR_EL3, ns_fiq_handler_addr); + write_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3), (ns_fiq_handler_addr)); /* * Mark this interrupt as complete to avoid a FIQ storm. */ irq = plat_ic_acknowledge_interrupt(); - if (irq < 1022) + if (irq < 1022U) { plat_ic_end_of_interrupt(irq); + } bakery_lock_release(&tegra_fiq_lock); @@ -79,27 +80,27 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id, ******************************************************************************/ void tegra_fiq_handler_setup(void) { - uint64_t flags; - int rc; + uint32_t flags; + int32_t rc; /* return if already registered */ - if (fiq_handler_active) - return; + if (fiq_handler_active == 0U) { + /* + * Register an interrupt handler for FIQ interrupts generated for + * NS interrupt sources + */ + flags = 0U; + set_interrupt_rm_flag((flags), (NON_SECURE)); + rc = register_interrupt_type_handler(INTR_TYPE_EL3, + tegra_fiq_interrupt_handler, + flags); + if (rc != 0) { + panic(); + } - /* - * Register an interrupt handler for FIQ interrupts generated for - * NS interrupt sources - */ - flags = 0; - set_interrupt_rm_flag(flags, NON_SECURE); - rc = register_interrupt_type_handler(INTR_TYPE_EL3, - tegra_fiq_interrupt_handler, - flags); - if (rc) - panic(); - - /* handler is now active */ - fiq_handler_active = 1; + /* handler is now active */ + fiq_handler_active = 1; + } } /******************************************************************************* @@ -113,26 +114,26 @@ void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint) /******************************************************************************* * Handler to return the NS EL1/EL0 CPU context ******************************************************************************/ -int tegra_fiq_get_intr_context(void) +int32_t tegra_fiq_get_intr_context(void) { cpu_context_t *ctx = cm_get_context(NON_SECURE); gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx); - el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx); - int cpu = plat_my_core_pos(); + const el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx); + uint32_t cpu = plat_my_core_pos(); uint64_t val; /* * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so * that el3_exit() sends these values back to the NS world. */ - write_ctx_reg(gpregs_ctx, CTX_GPREG_X0, fiq_state[cpu].elr_el3); - write_ctx_reg(gpregs_ctx, CTX_GPREG_X1, fiq_state[cpu].spsr_el3); + write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); + write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3)); - val = read_ctx_reg(gpregs_ctx, CTX_GPREG_SP_EL0); - write_ctx_reg(gpregs_ctx, CTX_GPREG_X2, val); + val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0)); + write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); - val = read_ctx_reg(el1state_ctx, CTX_SP_EL1); - write_ctx_reg(gpregs_ctx, CTX_GPREG_X3, val); + val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1)); + write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val)); return 0; }