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Merge pull request #1793 from marex/arm/master/fixes-v2.0.0 

Arm/master/fixes v2.0.0
This commit is contained in:
Antonio Niño Díaz 2019-01-31 10:22:36 +00:00 committed by GitHub
parent b57eb97262 c87c8f85b1
commit 5ce301b5cf
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 64 additions and 17 deletions
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4
drivers/renesas/rcar/cpld/ulcb_cpld.c
View File

@ -24,6 +24,9 @@
#define GPIO_INOUTSEL2 0xE6052004
#define GPIO_INOUTSEL6 0xE6055404
/* General IO/Interrupt Switching Register */
#define GPIO_IOINTSEL6 0xE6055400
/* GPIO/perihperal function select */
#define PFC_GPSR2 0xE6060108
#define PFC_GPSR6 0xE6060118
@ -93,6 +96,7 @@ static void cpld_init(void)
gpio_pfc(PFC_GPSR2, SSTBZ);
gpio_pfc(PFC_GPSR6, MOSI);
gpio_set_value(GPIO_IOINTSEL6, SCLK, 0);
gpio_set_value(GPIO_OUTDT6, SCLK, 0);
gpio_set_value(GPIO_OUTDT2, SSTBZ, 1);
gpio_set_value(GPIO_OUTDT6, MOSI, 0);

40
drivers/renesas/rcar/pwrc/pwrc.c
View File

@ -768,3 +768,43 @@ count_ca57:
done:
return count;
}
int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
{
uint64_t i;
uint64_t j;
uint64_t cpu_count;
uintptr_t reg_PSTR;
uint32_t status;
uint64_t my_cpu;
int32_t rtn;
uint32_t my_cluster_type;
const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = {
RCAR_CLUSTER_CA53,
RCAR_CLUSTER_CA57
};
const uintptr_t registerPSTR[PLATFORM_CLUSTER_COUNT] = {
RCAR_CA53PSTR,
RCAR_CA57PSTR
};
my_cluster_type = rcar_pwrc_get_cluster();
rtn = 0;
my_cpu = mpidr & ((uint64_t)(MPIDR_CPU_MASK));
for (i = 0U; i < ((uint64_t)(PLATFORM_CLUSTER_COUNT)); i++) {
cpu_count = rcar_pwrc_get_cpu_num(cluster_type[i]);
reg_PSTR = registerPSTR[i];
for (j = 0U; j < cpu_count; j++) {
if ((my_cluster_type != cluster_type[i]) || (my_cpu != j)) {
status = mmio_read_32(reg_PSTR) >> (j * 4U);
if ((status & 0x00000003U) == 0U) {
rtn--;
}
}
}
}
return (rtn);
}

1
drivers/renesas/rcar/pwrc/pwrc.h
View File

@ -44,6 +44,7 @@ void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr);
void rcar_pwrc_clusteroff(uint64_t mpidr);
void rcar_pwrc_cpuoff(uint64_t mpidr);
void rcar_pwrc_cpuon(uint64_t mpidr);
int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr);
void rcar_pwrc_setup(void);
uint32_t rcar_pwrc_get_cpu_wkr(uint64_t mpidr);

12
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
View File

@ -1137,13 +1137,13 @@ uint32_t recovery_from_backup_mode(void)
/* ddr backupmode end */
if (ddrBackup) {
NOTICE("[WARM_BOOT]");
NOTICE("BL2: [WARM_BOOT]\n");
} else {
NOTICE("[COLD_BOOT]");
NOTICE("BL2: [COLD_BOOT]\n");
} /* ddrBackup */
err = rcar_dram_update_boot_status(ddrBackup);
if (err) {
NOTICE("[BOOT_STATUS_UPDATE_ERROR]");
NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n");
return INITDRAM_ERR_I;
} /* err */
@ -1672,9 +1672,9 @@ int32_t rcar_dram_init(void)
md = *((volatile uint32_t*)RST_MODEMR);
ddr = (md & 0x00080000) >> 19;
if (ddr == 0x0) {
NOTICE("BL2: DDR1584(%s)", RCAR_E3_DDR_VERSION);
NOTICE("BL2: DDR1584(%s)\n", RCAR_E3_DDR_VERSION);
} else if(ddr == 0x1){
NOTICE("BL2: DDR1856(%s)", RCAR_E3_DDR_VERSION);
NOTICE("BL2: DDR1856(%s)\n", RCAR_E3_DDR_VERSION);
} /* ddr */
rcar_dram_get_boot_status(&ddrBackup);
@ -1691,8 +1691,6 @@ int32_t rcar_dram_init(void)
failcount = 1;
} /* dataL */
NOTICE("..%d\n", failcount); /* rev.0.05 */
if (failcount == 0) {
return INITDRAM_OK;
} else {

8
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
View File

@ -2826,7 +2826,7 @@ static uint32_t pll3_freq(uint32_t on)
set_freqchgack(0);
if (timeout) {
FATAL_MSG("Time out[2]");
FATAL_MSG("BL2: Time out[2]\n");
return (1);
}
return (0);
@ -3012,13 +3012,13 @@ static uint32_t init_ddr(void)
***********************************************************************/
#ifdef DDR_BACKUPMODE
if (ddrBackup) {
NOTICE("[WARM_BOOT]");
NOTICE("BL2: [WARM_BOOT]\n");
} else {
NOTICE("[COLD_BOOT]");
NOTICE("BL2: [COLD_BOOT]\n");
}
err = rcar_dram_update_boot_status(ddrBackup);
if (err) {
NOTICE("[BOOT_STATUS_UPDATE_ERROR]");
NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n");
return INITDRAM_ERR_I;
}
#endif

10
plat/renesas/rcar/bl2_cpg_init.c
View File

@ -28,7 +28,7 @@ static void bl2_realtime_cpg_init_m3n(void);
static void bl2_system_cpg_init_m3n(void);
#endif
#if (RCAR_LSI == RCAR_E3)
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
static void bl2_realtime_cpg_init_e3(void);
static void bl2_system_cpg_init_e3(void);
#endif
@ -193,7 +193,7 @@ static void bl2_system_cpg_init_m3n(void)
}
#endif
#if (RCAR_LSI == RCAR_E3)
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
static void bl2_realtime_cpg_init_e3(void)
{
/* Realtime Module Stop Control Registers */
@ -251,6 +251,9 @@ void bl2_cpg_init(void)
case RCAR_PRODUCT_M3N:
bl2_realtime_cpg_init_m3n();
break;
case RCAR_PRODUCT_E3:
bl2_realtime_cpg_init_e3();
break;
default:
panic();
break;
@ -284,6 +287,9 @@ void bl2_system_cpg_init(void)
case RCAR_PRODUCT_M3N:
bl2_system_cpg_init_m3n();
break;
case RCAR_PRODUCT_E3:
bl2_system_cpg_init_e3();
break;
default:
panic();
break;

2
plat/renesas/rcar/include/rcar_def.h
View File

@ -204,8 +204,6 @@
#define EXTAL_MD14_MD13_TYPE_3 U(16666600) /* MD14=1 MD13=1 */
#define EXTAL_SALVATOR_XS U(8320000) /* Salvator-XS */
#define EXTAL_EBISU U(24000000) /* Ebisu */
/* CPU Auxiliary Control Register */
#define RCAR_CA57_DIS_LOAD_PASS_STORE (ULL(1) << 55)
/* CPG write protect registers */
#define CPGWPR_PASSWORD (0x5A5AFFFFU)
#define CPGWPCR_PASSWORD (0xA5A50000U)

2
plat/renesas/rcar/plat_pm.c
View File

@ -175,7 +175,7 @@ static void __dead2 rcar_system_off(void)
uint64_t cpu = read_mpidr_el1() & 0x0000ffff;
int32_t rtn_on;
rtn_on = cpu_on_check(cpu);
rtn_on = rcar_pwrc_cpu_on_check(cpu);
if (cpu == rcar_boot_mpidr)
panic();

2
plat/renesas/rcar/platform.mk
View File

@ -4,7 +4,7 @@
# SPDX-License-Identifier: BSD-3-Clause
#
PROGRAMMABLE_RESET_ADDRESS := 1
PROGRAMMABLE_RESET_ADDRESS := 0
COLD_BOOT_SINGLE_CPU := 1
ARM_CCI_PRODUCT_ID := 500
TRUSTED_BOARD_BOOT := 1