andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

allwinner: Clean up CPU ops functions 

Convert them to take an mpidr instead of a (cluster, core) pair. This
simplifies all of the call sites, and actually makes the functions a bit
smaller.

Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland 2019-02-17 15:33:33 -06:00
parent 508116827c
commit 5d4bd66d2f
4 changed files with 30 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
plat/allwinner/common/include/sunxi_private.h
View File

@ -9,9 +9,9 @@
void sunxi_configure_mmu_el3(int flags);
void sunxi_cpu_on(unsigned int cluster, unsigned int core);
void sunxi_cpu_off(unsigned int cluster, unsigned int core);
void sunxi_disable_secondary_cpus(unsigned int primary_cpu);
void sunxi_cpu_on(u_register_t mpidr);
void sunxi_cpu_off(u_register_t mpidr);
void sunxi_disable_secondary_cpus(u_register_t primary_mpidr);
void __dead2 sunxi_power_down(void);
int sunxi_pmic_setup(uint16_t socid, const void *fdt);

3
plat/allwinner/common/sunxi_bl31_setup.c
View File

@ -11,6 +11,7 @@
#include <platform_def.h>
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/arm/gicv2.h>
#include <drivers/console.h>
@ -101,7 +102,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
/* Turn off all secondary CPUs */
sunxi_disable_secondary_cpus(plat_my_core_pos());
sunxi_disable_secondary_cpus(read_mpidr());
}
void bl31_plat_arch_setup(void)

34
plat/allwinner/common/sunxi_cpu_ops.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -45,9 +45,10 @@ static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core)
mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00);
}
void sunxi_cpu_off(unsigned int cluster, unsigned int core)
void sunxi_cpu_off(u_register_t mpidr)
{
int corenr = cluster * PLATFORM_MAX_CPUS_PER_CLUSTER + core;
unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core);
@ -55,9 +56,9 @@ void sunxi_cpu_off(unsigned int cluster, unsigned int core)
mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
/* We can't turn ourself off like this, but it works for other cores. */
if (plat_my_core_pos() != corenr) {
if (read_mpidr() != mpidr) {
/* Activate the core output clamps, but not for core 0. */
if (corenr != 0)
if (core != 0)
mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster),
BIT(core));
/* Assert CPU power-on reset */
@ -80,8 +81,11 @@ void sunxi_cpu_off(unsigned int cluster, unsigned int core)
0, BIT_32(core));
}
void sunxi_cpu_on(unsigned int cluster, unsigned int core)
void sunxi_cpu_on(u_register_t mpidr)
{
unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core);
/* Assert CPU core reset */
@ -102,12 +106,18 @@ void sunxi_cpu_on(unsigned int cluster, unsigned int core)
mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
}
void sunxi_disable_secondary_cpus(unsigned int primary_cpu)
void sunxi_disable_secondary_cpus(u_register_t primary_mpidr)
{
for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) {
if (cpu == primary_cpu)
continue;
sunxi_cpu_off(cpu / PLATFORM_MAX_CPUS_PER_CLUSTER,
cpu % PLATFORM_MAX_CPUS_PER_CLUSTER);
unsigned int cluster;
unsigned int core;
for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; ++cluster) {
for (core = 0; core < PLATFORM_MAX_CPUS_PER_CLUSTER; ++core) {
u_register_t mpidr = (cluster << MPIDR_AFF1_SHIFT) |
(core << MPIDR_AFF0_SHIFT) |
BIT(31);
if (mpidr != primary_mpidr)
sunxi_cpu_off(mpidr);
}
}
}

8
plat/allwinner/common/sunxi_pm.c
View File

@ -35,7 +35,7 @@ static int sunxi_pwr_domain_on(u_register_t mpidr)
if (mpidr_is_valid(mpidr) == 0)
return PSCI_E_INTERN_FAIL;
sunxi_cpu_on(MPIDR_AFFLVL1_VAL(mpidr), MPIDR_AFFLVL0_VAL(mpidr));
sunxi_cpu_on(mpidr);
return PSCI_E_SUCCESS;
}
@ -47,9 +47,7 @@ static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state)
{
u_register_t mpidr = read_mpidr();
sunxi_cpu_off(MPIDR_AFFLVL1_VAL(mpidr), MPIDR_AFFLVL0_VAL(mpidr));
sunxi_cpu_off(read_mpidr());
while (1)
wfi();
@ -64,7 +62,7 @@ static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
static void __dead2 sunxi_system_off(void)
{
/* Turn off all secondary CPUs */
sunxi_disable_secondary_cpus(plat_my_core_pos());
sunxi_disable_secondary_cpus(read_mpidr());
sunxi_power_down();
}