diff --git a/docs/plat/hikey960.rst b/docs/plat/hikey960.rst index aef012890..cd1880e1a 100644 --- a/docs/plat/hikey960.rst +++ b/docs/plat/hikey960.rst @@ -14,6 +14,9 @@ Code Locations - ARM Trusted Firmware: `link `__ +- OP-TEE: + `link `__ + - edk2: `link `__ @@ -62,7 +65,7 @@ Build Procedure EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey960/${BUILD_OPTION}_${AARCH64_TOOLCHAIN} cd ${EDK2_DIR} # Build UEFI & ARM Trust Firmware - ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware hikey960 + ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey960 # Generate l-loader.bin cd ${BUILD_PATH}/l-loader ln -sf ${EDK2_OUTPUT_DIR}/FV/bl1.bin diff --git a/plat/hisilicon/hikey960/aarch64/hikey960_common.c b/plat/hisilicon/hikey960/aarch64/hikey960_common.c index d7894b3e6..7068fb689 100644 --- a/plat/hisilicon/hikey960/aarch64/hikey960_common.c +++ b/plat/hisilicon/hikey960/aarch64/hikey960_common.c @@ -37,6 +37,10 @@ HIKEY960_UFS_DESC_SIZE, \ MT_MEMORY | MT_RW | MT_NS) +#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \ + TSP_SEC_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + /* * Table of regions for different BL stages to map using the MMU. * This doesn't include Trusted RAM as the 'mem_layout' argument passed to @@ -56,6 +60,7 @@ static const mmap_region_t hikey960_mmap[] = { static const mmap_region_t hikey960_mmap[] = { MAP_DDR, MAP_DEVICE, + MAP_TSP_MEM, {0} }; #endif @@ -63,6 +68,15 @@ static const mmap_region_t hikey960_mmap[] = { #if IMAGE_BL31 static const mmap_region_t hikey960_mmap[] = { MAP_DEVICE, + MAP_TSP_MEM, + {0} +}; +#endif + +#if IMAGE_BL32 +static const mmap_region_t hikey960_mmap[] = { + MAP_DEVICE, + MAP_DDR, {0} }; #endif diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c index e2257937e..de676a714 100644 --- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c @@ -177,6 +177,41 @@ void bl2_plat_set_bl31_ep_info(image_info_t *image, DISABLE_ALL_EXCEPTIONS); } +/******************************************************************************* + * Before calling this function BL32 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL32 and set SPSR and security state. + * On Hikey we only set the security state of the entrypoint + ******************************************************************************/ +#ifdef BL32_BASE +void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, + entry_point_info_t *bl32_ep_info) +{ + SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL32 image. + */ + bl32_ep_info->spsr = 0; +} + +/******************************************************************************* + * Populate the extents of memory available for loading BL32 + ******************************************************************************/ +void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) +{ + /* + * Populate the extents of memory available for loading BL32. + */ + bl32_meminfo->total_base = BL32_BASE; + bl32_meminfo->free_base = BL32_BASE; + bl32_meminfo->total_size = + (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; + bl32_meminfo->free_size = + (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; +} +#endif /* BL32_BASE */ + void bl2_plat_set_bl33_ep_info(image_info_t *image, entry_point_info_t *bl33_ep_info) { diff --git a/plat/hisilicon/hikey960/hikey960_def.h b/plat/hisilicon/hikey960/hikey960_def.h index e713e2e03..fc46d71a7 100644 --- a/plat/hisilicon/hikey960/hikey960_def.h +++ b/plat/hisilicon/hikey960/hikey960_def.h @@ -16,6 +16,25 @@ #define DEVICE_BASE 0xE0000000 #define DEVICE_SIZE 0x20000000 +/* Memory location options for TSP */ +#define HIKEY960_SRAM_ID 0 +#define HIKEY960_DRAM_ID 1 + +/* + * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several + * regions: + * - Secure DDR (default is the top 16MB) used by OP-TEE + * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) + * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature + * - Non-secure DDR (8MB) reserved for OP-TEE's future use + */ +#define DDR_SEC_SIZE 0x01000000 +#define DDR_SEC_BASE 0x3F000000 + +#define DDR_SDP_SIZE 0x00400000 +#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \ + DDR_SDP_SIZE) + /* * PL011 related constants */ diff --git a/plat/hisilicon/hikey960/hikey960_io_storage.c b/plat/hisilicon/hikey960/hikey960_io_storage.c index de54e8863..57d97e599 100644 --- a/plat/hisilicon/hikey960/hikey960_io_storage.c +++ b/plat/hisilicon/hikey960/hikey960_io_storage.c @@ -69,6 +69,10 @@ static const io_uuid_spec_t bl31_uuid_spec = { .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, }; +static const io_uuid_spec_t bl32_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32, +}; + static const io_uuid_spec_t bl33_uuid_spec = { .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, }; @@ -94,6 +98,11 @@ static const struct plat_io_policy policies[] = { (uintptr_t)&bl31_uuid_spec, check_fip }, + [BL32_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_uuid_spec, + check_fip + }, [BL33_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl33_uuid_spec, diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h index 369117b8a..8bf32c333 100644 --- a/plat/hisilicon/hikey960/include/platform_def.h +++ b/plat/hisilicon/hikey960/include/platform_def.h @@ -63,6 +63,27 @@ #define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */ #define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */ +/* + * BL3-2 specific defines. + */ + +/* + * The TSP currently executes from TZC secured area of DRAM. + */ +#define BL32_DRAM_BASE DDR_SEC_BASE +#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) + +#if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID) +#define TSP_SEC_MEM_BASE BL32_DRAM_BASE +#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) +#define BL32_BASE BL32_DRAM_BASE +#define BL32_LIMIT BL32_DRAM_LIMIT +#elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID) +#error "SRAM storage of TSP payload is currently unsupported" +#else +#error "Currently unsupported HIKEY960_TSP_LOCATION_ID value" +#endif + #define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */ #define NS_BL1U_SIZE (0x00100000) #define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) @@ -70,7 +91,7 @@ #define HIKEY960_NS_IMAGE_OFFSET (0x1AC18000) /* offset in l-loader */ #define HIKEY960_NS_TMP_OFFSET (0x1AE00000) -#define SCP_BL2_BASE BL31_BASE +#define SCP_BL2_BASE BL31_BASE /* 1AC5_8000 */ #define SCP_MEM_BASE (0x89C80000) #define SCP_MEM_SIZE (0x00040000) @@ -80,7 +101,7 @@ */ #define ADDR_SPACE_SIZE (1ull << 32) -#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31 +#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31 || IMAGE_BL32 #define MAX_XLAT_TABLES 3 #endif diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk index 722246c9d..edbce636e 100644 --- a/plat/hisilicon/hikey960/platform.mk +++ b/plat/hisilicon/hikey960/platform.mk @@ -4,11 +4,22 @@ # SPDX-License-Identifier: BSD-3-Clause # +# On Hikey960, the TSP can execute from TZC secure area in DRAM. +HIKEY960_TSP_RAM_LOCATION := dram +ifeq (${HIKEY960_TSP_RAM_LOCATION}, dram) + HIKEY960_TSP_RAM_LOCATION_ID = HIKEY960_DRAM_ID +else ifeq (${HIKEY960_TSP_RAM_LOCATION}, sram) + HIKEY960_TSP_RAM_LOCATION_ID := HIKEY960_SRAM_ID +else + $(error "Currently unsupported HIKEY960_TSP_RAM_LOCATION value") +endif + CRASH_CONSOLE_BASE := PL011_UART6_BASE COLD_BOOT_SINGLE_CPU := 1 PROGRAMMABLE_RESET_ADDRESS := 1 # Process flags +$(eval $(call add_define,HIKEY960_TSP_RAM_LOCATION_ID)) $(eval $(call add_define,CRASH_CONSOLE_BASE)) ENABLE_PLAT_COMPAT := 0