rcar_gen3: drivers: ddr-a: Synchronize tables
Synchronize the R-Car DDR-A driver, used on R-Car E3, with Renesas ATF release 2.0.0 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This commit is contained in:
parent
bd57db5316
commit
5e3c4bb0a4
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@ -57,14 +57,22 @@ uint32_t init_ddr(void)
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uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
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uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
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uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
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/* rev.0.10 */
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uint32_t pdr_ctl;
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/* rev.0.11 */
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uint32_t byp_ctl;
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/* rev.0.08 */
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if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
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pdqsr_ctl = 1;
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lcdl_ctl = 1;
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pdr_ctl = 1; /* rev.0.10 */
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byp_ctl = 1; /* rev.0.11 */
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}else {
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pdqsr_ctl = 0;
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lcdl_ctl = 0;
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pdr_ctl = 0; /* rev.0.10 */
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byp_ctl = 0; /* rev.0.11 */
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}
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/* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
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@ -198,6 +206,7 @@ uint32_t init_ddr(void)
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WriteReg_32(DBSC_E3_DBPDLK0,0x0000A55A);
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WriteReg_32(DBSC_E3_DBCMD,0x01840001);
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WriteReg_32(DBSC_E3_DBCMD,0x08840000);
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NOTICE("BL2: [COLD_BOOT]\n"); /* rev.0.11 */
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x80010000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
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@ -266,7 +275,11 @@ uint32_t init_ddr(void)
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while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
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if (byp_ctl == 1) {
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WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C720);
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} else {
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WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
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}
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
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while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
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@ -394,10 +407,6 @@ uint32_t init_ddr(void)
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
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while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
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/* rev.0.03 add Comment */
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/****************************************************************************
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* Initial_Step4( WLADJ training )
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***************************************************************************/
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for ( i = 0; i<4; i++){
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
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RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
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@ -426,6 +435,10 @@ uint32_t init_ddr(void)
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} /* RegVal_R6 */
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} /* for i */
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/* rev.0.10 move Comment */
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/****************************************************************************
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* Initial_Step4( WLADJ training )
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***************************************************************************/
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
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WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00C0);
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@ -443,14 +456,25 @@ uint32_t init_ddr(void)
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}
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/* PDR always off */ /* rev.0.10 */
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if (pdr_ctl == 1) {
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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}
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00010801);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
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while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
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/* rev.0.03 add Comment */
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/****************************************************************************
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* Initial_Step5678( RdWrbitRdWreye )
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* Initial_Step5(Read Data Bit Deskew)
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***************************************************************************/
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
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WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00D8);
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@ -472,11 +496,29 @@ if (pdqsr_ctl == 1){
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WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
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}
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/* PDR dynamic */ /* rev.0.10 */
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if (pdr_ctl == 1) {
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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}
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/****************************************************************************
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* Initial_Step6(Write Data Bit Deskew)
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***************************************************************************/
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
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while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
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/****************************************************************************
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* Initial_Step7(Read Data Eye Training)
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***************************************************************************/
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if (pdqsr_ctl == 1){
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
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@ -488,6 +530,18 @@ if (pdqsr_ctl == 1){
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WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
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}
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/* PDR always off */ /* rev.0.10 */
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if (pdr_ctl == 1) {
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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}
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
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@ -504,6 +558,21 @@ if (pdqsr_ctl == 1){
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WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
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}
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/* PDR dynamic */ /* rev.0.10 */
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if (pdr_ctl == 1) {
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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}
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/****************************************************************************
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* Initial_Step8(Write Data Eye Training)
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***************************************************************************/
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
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@ -528,10 +597,6 @@ if (pdqsr_ctl == 1){
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
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while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
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/* rev.0.03 add Comment */
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/****************************************************************************
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* Initial_Step5-2_7-2( Rd bit Rd eye )
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***************************************************************************/
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for ( i = 0; i < 4; i++){
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
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RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
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@ -561,6 +626,10 @@ if (pdqsr_ctl == 1){
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} /* RegVal_R12 < RegVal_R6 */
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} /* for i */
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/* rev.0.10 move Comment */
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/****************************************************************************
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* Initial_Step5-2_7-2( Rd bit Rd eye )
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***************************************************************************/
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/* rev.0.08 */
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if (pdqsr_ctl == 1){}else{
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@ -575,6 +644,18 @@ if (pdqsr_ctl == 1){
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}
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/* PDR always off */ /* rev.0.10 */
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if (pdr_ctl == 1) {
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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}
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
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@ -658,7 +739,11 @@ if (pdqsr_ctl == 1){
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
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if (byp_ctl == 1) {
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WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C720);
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} else {
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WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
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}
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
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while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
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@ -696,6 +781,17 @@ if (pdqsr_ctl == 1){
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}
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/* PDR dynamic */ /* rev.0.10 */
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if (pdr_ctl == 1) {
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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}
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/* rev.0.03 add Comment */
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/****************************************************************************
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@ -766,14 +862,22 @@ uint32_t recovery_from_backup_mode(void)
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uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
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uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
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uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
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/* rev.0.10 */
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uint32_t pdr_ctl;
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/* rev.0.11 */
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uint32_t byp_ctl;
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/* rev.0.08 */
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if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
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pdqsr_ctl = 1;
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lcdl_ctl = 1;
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pdr_ctl = 1; /* rev.0.10 */
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byp_ctl = 1; /* rev.0.11 */
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}else {
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pdqsr_ctl = 0;
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lcdl_ctl = 0;
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pdr_ctl = 0; /* rev.0.10 */
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byp_ctl = 0; /* rev.0.11 */
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}
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@ -908,7 +1012,11 @@ uint32_t recovery_from_backup_mode(void)
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000008); /* DDR_PLLCR */
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WriteReg_32(DBSC_E3_DBPDRGD0,0x000B8000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003); /* DDR_PGCR1 */
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WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
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if (byp_ctl == 1) {
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WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C720);
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} else {
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WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
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}
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000020); /* DDR_DXCCR */
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00181884);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x0000001A); /* DDR_ACIOCR0 */
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@ -1209,6 +1317,18 @@ uint32_t recovery_from_backup_mode(void)
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}
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/* PDR always off */ /* rev.0.10 */
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if (pdr_ctl == 1) {
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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}
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00010801);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
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@ -1235,6 +1355,18 @@ if (pdqsr_ctl == 1){
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WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
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}
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/* PDR dynamic */ /* rev.0.10 */
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if (pdr_ctl==1) {
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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}
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
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@ -1251,6 +1383,18 @@ if (pdqsr_ctl == 1){
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WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
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}
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/* PDR always off */ /* rev.0.10 */
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if (pdr_ctl == 1) {
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
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}
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
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@ -1267,6 +1411,18 @@ if (pdqsr_ctl == 1){
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WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
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}
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/* PDR dynamic */ /* rev.0.10 */
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if (pdr_ctl == 1) {
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
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WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
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WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
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||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
|
||||
}
|
||||
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
|
||||
|
@ -1331,6 +1487,18 @@ if (pdqsr_ctl == 1){
|
|||
|
||||
}
|
||||
|
||||
/* PDR always off */ /* rev.0.10 */
|
||||
if (pdr_ctl==1) {
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
|
||||
}
|
||||
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
|
||||
|
@ -1415,7 +1583,11 @@ if (pdqsr_ctl == 1){
|
|||
|
||||
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
|
||||
if (byp_ctl==1) {
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C720);
|
||||
} else {
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
|
||||
}
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
|
||||
while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
|
||||
|
@ -1444,6 +1616,18 @@ if (pdqsr_ctl == 1){
|
|||
|
||||
}
|
||||
|
||||
/* PDR dynamic */ /* rev.0.10 */
|
||||
if (pdr_ctl == 1) {
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
|
||||
WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
|
||||
WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
|
||||
}
|
||||
|
||||
|
||||
WriteReg_32(DBSC_E3_DBPDLK0,0x00000000);
|
||||
WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
#include <stdint.h>
|
||||
|
||||
#define RCAR_E3_DDR_VERSION "rev.0.09"
|
||||
#define RCAR_E3_DDR_VERSION "rev.0.11"
|
||||
|
||||
#ifdef ddr_qos_init_setting
|
||||
#define REFRESH_RATE 3900 /* Average periodic refresh interval[ns]. Support 3900,7800 */
|
||||
|
|
Loading…
Reference in New Issue