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Merge pull request #1504 from hzhuang1/migrate_mmc 

Migrate mmc
This commit is contained in:
Dimitris Papastamos 2018-08-10 12:40:53 +01:00 committed by GitHub
parent 8ae41aec32 fcda63ba45
commit 5e4c590d84
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
16 changed files with 103 additions and 619 deletions
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363
drivers/emmc/emmc.c
View File

@ -1,363 +0,0 @@
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Defines a simple and generic interface to access eMMC device.
*/
#include <arch_helpers.h>
#include <assert.h>
#include <debug.h>
#include <emmc.h>
#include <errno.h>
#include <string.h>
#include <utils.h>
static const emmc_ops_t *ops;
static unsigned int emmc_ocr_value;
static emmc_csd_t emmc_csd;
static unsigned int emmc_flags;
static int is_cmd23_enabled(void)
{
return (!!(emmc_flags & EMMC_FLAG_CMD23));
}
static int emmc_device_state(void)
{
emmc_cmd_t cmd;
int ret;
do {
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD13;
cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
cmd.resp_type = EMMC_RESPONSE_R1;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
assert((cmd.resp_data[0] & STATUS_SWITCH_ERROR) == 0);
/* Ignore improbable errors in release builds */
(void)ret;
} while ((cmd.resp_data[0] & STATUS_READY_FOR_DATA) == 0);
return EMMC_GET_STATE(cmd.resp_data[0]);
}
static void emmc_set_ext_csd(unsigned int ext_cmd, unsigned int value)
{
emmc_cmd_t cmd;
int ret, state;
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD6;
cmd.cmd_arg = EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) |
EXTCSD_VALUE(value) | 1;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
/* wait to exit PRG state */
do {
state = emmc_device_state();
} while (state == EMMC_STATE_PRG);
/* Ignore improbable errors in release builds */
(void)ret;
}
static void emmc_set_ios(int clk, int bus_width)
{
int ret;
/* set IO speed & IO bus width */
if (emmc_csd.spec_vers == 4)
emmc_set_ext_csd(CMD_EXTCSD_BUS_WIDTH, bus_width);
ret = ops->set_ios(clk, bus_width);
assert(ret == 0);
/* Ignore improbable errors in release builds */
(void)ret;
}
static int emmc_enumerate(int clk, int bus_width)
{
emmc_cmd_t cmd;
int ret, state;
ops->init();
/* CMD0: reset to IDLE */
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD0;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
while (1) {
/* CMD1: get OCR register */
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD1;
cmd.cmd_arg = OCR_SECTOR_MODE | OCR_VDD_MIN_2V7 |
OCR_VDD_MIN_1V7;
cmd.resp_type = EMMC_RESPONSE_R3;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
emmc_ocr_value = cmd.resp_data[0];
if (emmc_ocr_value & OCR_POWERUP)
break;
}
/* CMD2: Card Identification */
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD2;
cmd.resp_type = EMMC_RESPONSE_R2;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
/* CMD3: Set Relative Address */
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD3;
cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
cmd.resp_type = EMMC_RESPONSE_R1;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
/* CMD9: CSD Register */
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD9;
cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
cmd.resp_type = EMMC_RESPONSE_R2;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
memcpy(&emmc_csd, &cmd.resp_data, sizeof(cmd.resp_data));
/* CMD7: Select Card */
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD7;
cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
cmd.resp_type = EMMC_RESPONSE_R1;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
/* wait to TRAN state */
do {
state = emmc_device_state();
} while (state != EMMC_STATE_TRAN);
emmc_set_ios(clk, bus_width);
return ret;
}
size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size)
{
emmc_cmd_t cmd;
int ret;
assert((ops != 0) &&
(ops->read != 0) &&
((buf & EMMC_BLOCK_MASK) == 0) &&
((size & EMMC_BLOCK_MASK) == 0));
inv_dcache_range(buf, size);
ret = ops->prepare(lba, buf, size);
assert(ret == 0);
if (is_cmd23_enabled()) {
zeromem(&cmd, sizeof(emmc_cmd_t));
/* set block count */
cmd.cmd_idx = EMMC_CMD23;
cmd.cmd_arg = size / EMMC_BLOCK_SIZE;
cmd.resp_type = EMMC_RESPONSE_R1;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD18;
} else {
if (size > EMMC_BLOCK_SIZE)
cmd.cmd_idx = EMMC_CMD18;
else
cmd.cmd_idx = EMMC_CMD17;
}
if ((emmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE)
cmd.cmd_arg = lba * EMMC_BLOCK_SIZE;
else
cmd.cmd_arg = lba;
cmd.resp_type = EMMC_RESPONSE_R1;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
ret = ops->read(lba, buf, size);
assert(ret == 0);
/* wait buffer empty */
emmc_device_state();
if (is_cmd23_enabled() == 0) {
if (size > EMMC_BLOCK_SIZE) {
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD12;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
}
}
/* Ignore improbable errors in release builds */
(void)ret;
return size;
}
size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size)
{
emmc_cmd_t cmd;
int ret;
assert((ops != 0) &&
(ops->write != 0) &&
((buf & EMMC_BLOCK_MASK) == 0) &&
((size & EMMC_BLOCK_MASK) == 0));
clean_dcache_range(buf, size);
ret = ops->prepare(lba, buf, size);
assert(ret == 0);
if (is_cmd23_enabled()) {
/* set block count */
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD23;
cmd.cmd_arg = size / EMMC_BLOCK_SIZE;
cmd.resp_type = EMMC_RESPONSE_R1;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD25;
} else {
zeromem(&cmd, sizeof(emmc_cmd_t));
if (size > EMMC_BLOCK_SIZE)
cmd.cmd_idx = EMMC_CMD25;
else
cmd.cmd_idx = EMMC_CMD24;
}
if ((emmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE)
cmd.cmd_arg = lba * EMMC_BLOCK_SIZE;
else
cmd.cmd_arg = lba;
cmd.resp_type = EMMC_RESPONSE_R1;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
ret = ops->write(lba, buf, size);
assert(ret == 0);
/* wait buffer empty */
emmc_device_state();
if (is_cmd23_enabled() == 0) {
if (size > EMMC_BLOCK_SIZE) {
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD12;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
}
}
/* Ignore improbable errors in release builds */
(void)ret;
return size;
}
size_t emmc_erase_blocks(int lba, size_t size)
{
emmc_cmd_t cmd;
int ret, state;
assert(ops != 0);
assert((size != 0) && ((size % EMMC_BLOCK_SIZE) == 0));
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD35;
cmd.cmd_arg = lba;
cmd.resp_type = EMMC_RESPONSE_R1;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD36;
cmd.cmd_arg = lba + (size / EMMC_BLOCK_SIZE) - 1;
cmd.resp_type = EMMC_RESPONSE_R1;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
zeromem(&cmd, sizeof(emmc_cmd_t));
cmd.cmd_idx = EMMC_CMD38;
cmd.resp_type = EMMC_RESPONSE_R1B;
ret = ops->send_cmd(&cmd);
assert(ret == 0);
/* wait to TRAN state */
do {
state = emmc_device_state();
} while (state != EMMC_STATE_TRAN);
/* Ignore improbable errors in release builds */
(void)ret;
return size;
}
static inline void emmc_rpmb_enable(void)
{
emmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
PART_CFG_BOOT_PARTITION1_ENABLE |
PART_CFG_PARTITION1_ACCESS);
}
static inline void emmc_rpmb_disable(void)
{
emmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
PART_CFG_BOOT_PARTITION1_ENABLE);
}
size_t emmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size)
{
size_t size_read;
emmc_rpmb_enable();
size_read = emmc_read_blocks(lba, buf, size);
emmc_rpmb_disable();
return size_read;
}
size_t emmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size)
{
size_t size_written;
emmc_rpmb_enable();
size_written = emmc_write_blocks(lba, buf, size);
emmc_rpmb_disable();
return size_written;
}
size_t emmc_rpmb_erase_blocks(int lba, size_t size)
{
size_t size_erased;
emmc_rpmb_enable();
size_erased = emmc_erase_blocks(lba, size);
emmc_rpmb_disable();
return size_erased;
}
void emmc_init(const emmc_ops_t *ops_ptr, int clk, int width,
unsigned int flags)
{
assert((ops_ptr != 0) &&
(ops_ptr->init != 0) &&
(ops_ptr->send_cmd != 0) &&
(ops_ptr->set_ios != 0) &&
(ops_ptr->prepare != 0) &&
(ops_ptr->read != 0) &&
(ops_ptr->write != 0) &&
(clk != 0) &&
((width == EMMC_BUS_WIDTH_1) ||
(width == EMMC_BUS_WIDTH_4) ||
(width == EMMC_BUS_WIDTH_8) ||
(width == EMMC_BUS_WIDTH_DDR_4) ||
(width == EMMC_BUS_WIDTH_DDR_8)));
ops = ops_ptr;
emmc_flags = flags;
emmc_enumerate(clk, width);
}

36
drivers/mmc/mmc.c
View File

@ -24,7 +24,7 @@
static const struct mmc_ops *ops;
static unsigned int mmc_ocr_value;
static struct mmc_csd_emmc mmc_csd;
static unsigned char mmc_ext_csd[512] __aligned(4);
static unsigned char mmc_ext_csd[512] __aligned(16);
static unsigned int mmc_flags;
static struct mmc_device_info *mmc_dev_info;
static unsigned int rca;
@ -363,8 +363,6 @@ static int mmc_reset_to_idle(void)
{
int ret;
mdelay(1);
/* CMD0: reset to IDLE */
ret = mmc_send_cmd(MMC_CMD(0), 0, 0, NULL);
if (ret != 0) {
@ -413,14 +411,16 @@ static int mmc_enumerate(unsigned int clk, unsigned int bus_width)
mmc_reset_to_idle();
/* CMD8: Send Interface Condition Command */
ret = mmc_send_cmd(MMC_CMD(8), VHS_2_7_3_6_V | CMD8_CHECK_PATTERN,
MMC_RESPONSE_R(7), &resp_data[0]);
if ((ret == 0) && ((resp_data[0] & 0xffU) == CMD8_CHECK_PATTERN)) {
ret = sd_send_op_cond();
} else {
if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
ret = mmc_send_op_cond();
} else {
/* CMD8: Send Interface Condition Command */
ret = mmc_send_cmd(MMC_CMD(8), VHS_2_7_3_6_V | CMD8_CHECK_PATTERN,
MMC_RESPONSE_R(7), &resp_data[0]);
if ((ret == 0) && ((resp_data[0] & 0xffU) == CMD8_CHECK_PATTERN)) {
ret = sd_send_op_cond();
}
}
if (ret != 0) {
return ret;
@ -473,15 +473,15 @@ static int mmc_enumerate(unsigned int clk, unsigned int bus_width)
}
} while (ret != MMC_STATE_TRAN);
ret = mmc_fill_device_info();
ret = mmc_set_ios(clk, bus_width);
if (ret != 0) {
return ret;
}
return mmc_set_ios(clk, bus_width);
return mmc_fill_device_info();
}
size_t mmc_read_blocks(unsigned int lba, uintptr_t buf, size_t size)
size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size)
{
int ret;
unsigned int cmd_idx, cmd_arg;
@ -548,7 +548,7 @@ size_t mmc_read_blocks(unsigned int lba, uintptr_t buf, size_t size)
return size;
}
size_t mmc_write_blocks(unsigned int lba, const uintptr_t buf, size_t size)
size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size)
{
int ret;
unsigned int cmd_idx, cmd_arg;
@ -615,7 +615,7 @@ size_t mmc_write_blocks(unsigned int lba, const uintptr_t buf, size_t size)
return size;
}
size_t mmc_erase_blocks(unsigned int lba, size_t size)
size_t mmc_erase_blocks(int lba, size_t size)
{
int ret;
@ -661,7 +661,7 @@ static inline void mmc_rpmb_disable(void)
PART_CFG_BOOT_PARTITION1_ENABLE);
}
size_t mmc_rpmb_read_blocks(unsigned int lba, uintptr_t buf, size_t size)
size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size)
{
size_t size_read;
@ -672,7 +672,7 @@ size_t mmc_rpmb_read_blocks(unsigned int lba, uintptr_t buf, size_t size)
return size_read;
}
size_t mmc_rpmb_write_blocks(unsigned int lba, const uintptr_t buf, size_t size)
size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size)
{
size_t size_written;
@ -683,7 +683,7 @@ size_t mmc_rpmb_write_blocks(unsigned int lba, const uintptr_t buf, size_t size)
return size_written;
}
size_t mmc_rpmb_erase_blocks(unsigned int lba, size_t size)
size_t mmc_rpmb_erase_blocks(int lba, size_t size)
{
size_t size_erased;

78
drivers/synopsys/emmc/dw_mmc.c
View File

@ -10,8 +10,8 @@
#include <debug.h>
#include <delay_timer.h>
#include <dw_mmc.h>
#include <emmc.h>
#include <errno.h>
#include <mmc.h>
#include <mmio.h>
#include <string.h>
@ -107,6 +107,8 @@
#define DWMMC_8BIT_MODE (1 << 6)
#define DWMMC_ADDRESS_MASK U(0x0f)
#define TIMEOUT 100000
struct dw_idmac_desc {
@ -117,13 +119,13 @@ struct dw_idmac_desc {
};
static void dw_init(void);
static int dw_send_cmd(emmc_cmd_t *cmd);
static int dw_set_ios(int clk, int width);
static int dw_send_cmd(struct mmc_cmd *cmd);
static int dw_set_ios(unsigned int clk, unsigned int width);
static int dw_prepare(int lba, uintptr_t buf, size_t size);
static int dw_read(int lba, uintptr_t buf, size_t size);
static int dw_write(int lba, uintptr_t buf, size_t size);
static const emmc_ops_t dw_mmc_ops = {
static const struct mmc_ops dw_mmc_ops = {
.init = dw_init,
.send_cmd = dw_send_cmd,
.set_ios = dw_set_ios,
@ -187,7 +189,7 @@ static void dw_init(void)
unsigned int data;
uintptr_t base;
assert((dw_params.reg_base & EMMC_BLOCK_MASK) == 0);
assert((dw_params.reg_base & MMC_BLOCK_MASK) == 0);
base = dw_params.reg_base;
mmio_write_32(base + DWMMC_PWREN, 1);
@ -203,7 +205,7 @@ static void dw_init(void)
mmio_write_32(base + DWMMC_INTMASK, 0);
mmio_write_32(base + DWMMC_TMOUT, ~0);
mmio_write_32(base + DWMMC_IDINTEN, ~0);
mmio_write_32(base + DWMMC_BLKSIZ, EMMC_BLOCK_SIZE);
mmio_write_32(base + DWMMC_BLKSIZ, MMC_BLOCK_SIZE);
mmio_write_32(base + DWMMC_BYTCNT, 256 * 1024);
mmio_write_32(base + DWMMC_DEBNCE, 0x00ffffff);
mmio_write_32(base + DWMMC_BMOD, BMOD_SWRESET);
@ -215,11 +217,11 @@ static void dw_init(void)
mmio_write_32(base + DWMMC_BMOD, data);
udelay(100);
dw_set_clk(EMMC_BOOT_CLK_RATE);
dw_set_clk(MMC_BOOT_CLK_RATE);
udelay(100);
}
static int dw_send_cmd(emmc_cmd_t *cmd)
static int dw_send_cmd(struct mmc_cmd *cmd)
{
unsigned int op, data, err_mask;
uintptr_t base;
@ -230,22 +232,22 @@ static int dw_send_cmd(emmc_cmd_t *cmd)
base = dw_params.reg_base;
switch (cmd->cmd_idx) {
case EMMC_CMD0:
case 0:
op = CMD_SEND_INIT;
break;
case EMMC_CMD12:
case 12:
op = CMD_STOP_ABORT_CMD;
break;
case EMMC_CMD13:
case 13:
op = CMD_WAIT_PRVDATA_COMPLETE;
break;
case EMMC_CMD8:
case EMMC_CMD17:
case EMMC_CMD18:
case 8:
case 17:
case 18:
op = CMD_DATA_TRANS_EXPECT | CMD_WAIT_PRVDATA_COMPLETE;
break;
case EMMC_CMD24:
case EMMC_CMD25:
case 24:
case 25:
op = CMD_WRITE | CMD_DATA_TRANS_EXPECT |
CMD_WAIT_PRVDATA_COMPLETE;
break;
@ -257,11 +259,11 @@ static int dw_send_cmd(emmc_cmd_t *cmd)
switch (cmd->resp_type) {
case 0:
break;
case EMMC_RESPONSE_R2:
case MMC_RESPONSE_R(2):
op |= CMD_RESP_EXPECT | CMD_CHECK_RESP_CRC |
CMD_RESP_LEN;
break;
case EMMC_RESPONSE_R3:
case MMC_RESPONSE_R(3):
op |= CMD_RESP_EXPECT;
break;
default:
@ -307,16 +309,16 @@ static int dw_send_cmd(emmc_cmd_t *cmd)
return 0;
}
static int dw_set_ios(int clk, int width)
static int dw_set_ios(unsigned int clk, unsigned int width)
{
switch (width) {
case EMMC_BUS_WIDTH_1:
case MMC_BUS_WIDTH_1:
mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_1BIT);
break;
case EMMC_BUS_WIDTH_4:
case MMC_BUS_WIDTH_4:
mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_4BIT);
break;
case EMMC_BUS_WIDTH_8:
case MMC_BUS_WIDTH_8:
mmio_write_32(dw_params.reg_base + DWMMC_CTYPE, CTYPE_8BIT);
break;
default:
@ -333,12 +335,14 @@ static int dw_prepare(int lba, uintptr_t buf, size_t size)
int desc_cnt, i, last;
uintptr_t base;
assert(((buf & EMMC_BLOCK_MASK) == 0) &&
((size % EMMC_BLOCK_SIZE) == 0) &&
assert(((buf & DWMMC_ADDRESS_MASK) == 0) &&
((size % MMC_BLOCK_SIZE) == 0) &&
(dw_params.desc_size > 0) &&
((dw_params.reg_base & EMMC_BLOCK_MASK) == 0) &&
((dw_params.desc_base & EMMC_BLOCK_MASK) == 0) &&
((dw_params.desc_size & EMMC_BLOCK_MASK) == 0));
((dw_params.reg_base & MMC_BLOCK_MASK) == 0) &&
((dw_params.desc_base & MMC_BLOCK_MASK) == 0) &&
((dw_params.desc_size & MMC_BLOCK_MASK) == 0));
flush_dcache_range(buf, size);
desc_cnt = (size + DWMMC_DMA_MAX_BUFFER_SIZE - 1) /
DWMMC_DMA_MAX_BUFFER_SIZE;
@ -367,7 +371,7 @@ static int dw_prepare(int lba, uintptr_t buf, size_t size)
(desc + last)->des3 = 0;
mmio_write_32(base + DWMMC_DBADDR, dw_params.desc_base);
clean_dcache_range(dw_params.desc_base,
flush_dcache_range(dw_params.desc_base,
desc_cnt * DWMMC_DMA_MAX_BUFFER_SIZE);
return 0;
@ -383,19 +387,19 @@ static int dw_write(int lba, uintptr_t buf, size_t size)
return 0;
}
void dw_mmc_init(dw_mmc_params_t *params)
void dw_mmc_init(dw_mmc_params_t *params, struct mmc_device_info *info)
{
assert((params != 0) &&
((params->reg_base & EMMC_BLOCK_MASK) == 0) &&
((params->desc_base & EMMC_BLOCK_MASK) == 0) &&
((params->desc_size & EMMC_BLOCK_MASK) == 0) &&
((params->reg_base & MMC_BLOCK_MASK) == 0) &&
((params->desc_base & MMC_BLOCK_MASK) == 0) &&
((params->desc_size & MMC_BLOCK_MASK) == 0) &&
(params->desc_size > 0) &&
(params->clk_rate > 0) &&
((params->bus_width == EMMC_BUS_WIDTH_1) ||
(params->bus_width == EMMC_BUS_WIDTH_4) ||
(params->bus_width == EMMC_BUS_WIDTH_8)));
((params->bus_width == MMC_BUS_WIDTH_1) ||
(params->bus_width == MMC_BUS_WIDTH_4) ||
(params->bus_width == MMC_BUS_WIDTH_8)));
memcpy(&dw_params, params, sizeof(dw_mmc_params_t));
emmc_init(&dw_mmc_ops, params->clk_rate, params->bus_width,
params->flags);
mmc_init(&dw_mmc_ops, params->clk_rate, params->bus_width,
params->flags, info);
}

165
include/drivers/emmc.h
View File

@ -1,165 +0,0 @@
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EMMC_H__
#define __EMMC_H__
#include <stdint.h>
#define EMMC_BLOCK_SIZE 512
#define EMMC_BLOCK_MASK (EMMC_BLOCK_SIZE - 1)
#define EMMC_BOOT_CLK_RATE (400 * 1000)
#define EMMC_CMD0 0
#define EMMC_CMD1 1
#define EMMC_CMD2 2
#define EMMC_CMD3 3
#define EMMC_CMD6 6
#define EMMC_CMD7 7
#define EMMC_CMD8 8
#define EMMC_CMD9 9
#define EMMC_CMD12 12
#define EMMC_CMD13 13
#define EMMC_CMD17 17
#define EMMC_CMD18 18
#define EMMC_CMD21 21
#define EMMC_CMD23 23
#define EMMC_CMD24 24
#define EMMC_CMD25 25
#define EMMC_CMD35 35
#define EMMC_CMD36 36
#define EMMC_CMD38 38
#define OCR_POWERUP (1 << 31)
#define OCR_BYTE_MODE (0 << 29)
#define OCR_SECTOR_MODE (2 << 29)
#define OCR_ACCESS_MODE_MASK (3 << 29)
#define OCR_VDD_MIN_2V7 (0x1ff << 15)
#define OCR_VDD_MIN_2V0 (0x7f << 8)
#define OCR_VDD_MIN_1V7 (1 << 7)
#define EMMC_RESPONSE_R1 1
#define EMMC_RESPONSE_R1B 1
#define EMMC_RESPONSE_R2 4
#define EMMC_RESPONSE_R3 1
#define EMMC_RESPONSE_R4 1
#define EMMC_RESPONSE_R5 1
#define EMMC_FIX_RCA 6 /* > 1 */
#define RCA_SHIFT_OFFSET 16
#define CMD_EXTCSD_PARTITION_CONFIG 179
#define CMD_EXTCSD_BUS_WIDTH 183
#define CMD_EXTCSD_HS_TIMING 185
#define PART_CFG_BOOT_PARTITION1_ENABLE (1 << 3)
#define PART_CFG_PARTITION1_ACCESS (1 << 0)
/* values in EXT CSD register */
#define EMMC_BUS_WIDTH_1 0
#define EMMC_BUS_WIDTH_4 1
#define EMMC_BUS_WIDTH_8 2
#define EMMC_BUS_WIDTH_DDR_4 5
#define EMMC_BUS_WIDTH_DDR_8 6
#define EMMC_BOOT_MODE_BACKWARD (0 << 3)
#define EMMC_BOOT_MODE_HS_TIMING (1 << 3)
#define EMMC_BOOT_MODE_DDR (2 << 3)
#define EXTCSD_SET_CMD (0 << 24)
#define EXTCSD_SET_BITS (1 << 24)
#define EXTCSD_CLR_BITS (2 << 24)
#define EXTCSD_WRITE_BYTES (3 << 24)
#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
#define STATUS_READY_FOR_DATA (1 << 8)
#define STATUS_SWITCH_ERROR (1 << 7)
#define EMMC_GET_STATE(x) (((x) >> 9) & 0xf)
#define EMMC_STATE_IDLE 0
#define EMMC_STATE_READY 1
#define EMMC_STATE_IDENT 2
#define EMMC_STATE_STBY 3
#define EMMC_STATE_TRAN 4
#define EMMC_STATE_DATA 5
#define EMMC_STATE_RCV 6
#define EMMC_STATE_PRG 7
#define EMMC_STATE_DIS 8
#define EMMC_STATE_BTST 9
#define EMMC_STATE_SLP 10
#define EMMC_FLAG_CMD23 (1 << 0)
typedef struct emmc_cmd {
unsigned int cmd_idx;
unsigned int cmd_arg;
unsigned int resp_type;
unsigned int resp_data[4];
} emmc_cmd_t;
typedef struct emmc_ops {
void (*init)(void);
int (*send_cmd)(emmc_cmd_t *cmd);
int (*set_ios)(int clk, int width);
int (*prepare)(int lba, uintptr_t buf, size_t size);
int (*read)(int lba, uintptr_t buf, size_t size);
int (*write)(int lba, const uintptr_t buf, size_t size);
} emmc_ops_t;
typedef struct emmc_csd {
unsigned int not_used: 1;
unsigned int crc: 7;
unsigned int ecc: 2;
unsigned int file_format: 2;
unsigned int tmp_write_protect: 1;
unsigned int perm_write_protect: 1;
unsigned int copy: 1;
unsigned int file_format_grp: 1;
unsigned int reserved_1: 5;
unsigned int write_bl_partial: 1;
unsigned int write_bl_len: 4;
unsigned int r2w_factor: 3;
unsigned int default_ecc: 2;
unsigned int wp_grp_enable: 1;
unsigned int wp_grp_size: 5;
unsigned int erase_grp_mult: 5;
unsigned int erase_grp_size: 5;
unsigned int c_size_mult: 3;
unsigned int vdd_w_curr_max: 3;
unsigned int vdd_w_curr_min: 3;
unsigned int vdd_r_curr_max: 3;
unsigned int vdd_r_curr_min: 3;
unsigned int c_size_low: 2;
unsigned int c_size_high: 10;
unsigned int reserved_2: 2;
unsigned int dsr_imp: 1;
unsigned int read_blk_misalign: 1;
unsigned int write_blk_misalign: 1;
unsigned int read_bl_partial: 1;
unsigned int read_bl_len: 4;
unsigned int ccc: 12;
unsigned int tran_speed: 8;
unsigned int nsac: 8;
unsigned int taac: 8;
unsigned int reserved_3: 2;
unsigned int spec_vers: 4;
unsigned int csd_structure: 2;
} emmc_csd_t;
size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size);
size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size);
size_t emmc_erase_blocks(int lba, size_t size);
size_t emmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
size_t emmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
size_t emmc_rpmb_erase_blocks(int lba, size_t size);
void emmc_init(const emmc_ops_t *ops, int clk, int bus_width,
unsigned int flags);
#endif /* __EMMC_H__ */

13
include/drivers/mmc.h
View File

@ -208,13 +208,12 @@ struct mmc_device_info {
enum mmc_device_type mmc_dev_type; /* Type of MMC */
};
size_t mmc_read_blocks(unsigned int lba, uintptr_t buf, size_t size);
size_t mmc_write_blocks(unsigned int lba, const uintptr_t buf, size_t size);
size_t mmc_erase_blocks(unsigned int lba, size_t size);
size_t mmc_rpmb_read_blocks(unsigned int lba, uintptr_t buf, size_t size);
size_t mmc_rpmb_write_blocks(unsigned int lba, const uintptr_t buf,
size_t size);
size_t mmc_rpmb_erase_blocks(unsigned int lba, size_t size);
size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size);
size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size);
size_t mmc_erase_blocks(int lba, size_t size);
size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
size_t mmc_rpmb_erase_blocks(int lba, size_t size);
int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
unsigned int width, unsigned int flags,
struct mmc_device_info *device_info);

4
include/drivers/synopsys/dw_mmc.h
View File

@ -7,6 +7,8 @@
#ifndef __DW_MMC_H__
#define __DW_MMC_H__
#include <mmc.h>
typedef struct dw_mmc_params {
uintptr_t reg_base;
uintptr_t desc_base;
@ -16,6 +18,6 @@ typedef struct dw_mmc_params {
unsigned int flags;
} dw_mmc_params_t;
void dw_mmc_init(dw_mmc_params_t *params);
void dw_mmc_init(dw_mmc_params_t *params, struct mmc_device_info *info);
#endif /* __DW_MMC_H__ */

2
maintainers.rst
View File

@ -34,13 +34,11 @@ eMMC/UFS drivers
----------------
:M: Haojian Zhuang <haojian.zhuang@linaro.org>
:G: `hzhuang1`_
:F: drivers/emmc/
:F: drivers/partition/
:F: drivers/synopsys/emmc/
:F: drivers/synopsys/ufs/
:F: drivers/ufs/
:F: include/drivers/dw_ufs.h
:F: include/drivers/emmc.h
:F: include/drivers/ufs.h
:F: include/drivers/synopsys/dw_mmc.h

10
plat/hisilicon/hikey/hikey_bl1_setup.c
View File

@ -10,11 +10,11 @@
#include <console.h>
#include <debug.h>
#include <dw_mmc.h>
#include <emmc.h>
#include <errno.h>
#include <hi6220.h>
#include <hikey_def.h>
#include <hikey_layout.h>
#include <mmc.h>
#include <mmio.h>
#include <platform.h>
#include <string.h>
@ -97,6 +97,7 @@ void bl1_plat_arch_setup(void)
void bl1_platform_setup(void)
{
dw_mmc_params_t params;
struct mmc_device_info info;
assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) &&
((SRAM_BASE + SRAM_SIZE) >=
@ -115,9 +116,10 @@ void bl1_platform_setup(void)
params.desc_base = HIKEY_BL1_MMC_DESC_BASE;
params.desc_size = 1 << 20;
params.clk_rate = 24 * 1000 * 1000;
params.bus_width = EMMC_BUS_WIDTH_8;
params.flags = EMMC_FLAG_CMD23;
dw_mmc_init(&params);
params.bus_width = MMC_BUS_WIDTH_8;
params.flags = MMC_FLAG_CMD23;
info.mmc_dev_type = MMC_IS_EMMC;
dw_mmc_init(&params, &info);
hikey_io_setup();
}

10
plat/hisilicon/hikey/hikey_bl2_setup.c
View File

@ -11,11 +11,11 @@
#include <debug.h>
#include <desc_image_load.h>
#include <dw_mmc.h>
#include <emmc.h>
#include <errno.h>
#include <hi6220.h>
#include <hisi_mcu.h>
#include <hisi_sram_map.h>
#include <mmc.h>
#include <mmio.h>
#ifdef SPD_opteed
#include <optee_utils.h>
@ -299,6 +299,7 @@ void bl2_el3_plat_arch_setup(void)
void bl2_platform_setup(void)
{
dw_mmc_params_t params;
struct mmc_device_info info;
hikey_sp804_init();
hikey_gpio_init();
@ -328,9 +329,10 @@ void bl2_platform_setup(void)
params.desc_base = HIKEY_MMC_DESC_BASE;
params.desc_size = 1 << 20;
params.clk_rate = 24 * 1000 * 1000;
params.bus_width = EMMC_BUS_WIDTH_8;
params.flags = EMMC_FLAG_CMD23;
dw_mmc_init(&params);
params.bus_width = MMC_BUS_WIDTH_8;
params.flags = MMC_FLAG_CMD23;
info.mmc_dev_type = MMC_IS_EMMC;
dw_mmc_init(&params, &info);
hikey_io_setup();
}

8
plat/hisilicon/hikey/hikey_io_storage.c
View File

@ -7,7 +7,6 @@
#include <arch_helpers.h>
#include <assert.h>
#include <debug.h>
#include <emmc.h>
#include <errno.h>
#include <firmware_image_package.h>
#include <io_block.h>
@ -15,6 +14,7 @@
#include <io_fip.h>
#include <io_memmap.h>
#include <io_storage.h>
#include <mmc.h>
#include <mmio.h>
#include <platform_def.h>
#include <semihosting.h> /* For FOPEN_MODE_... */
@ -59,10 +59,10 @@ static const io_block_dev_spec_t emmc_dev_spec = {
},
#endif
.ops = {
.read = emmc_read_blocks,
.write = emmc_write_blocks,
.read = mmc_read_blocks,
.write = mmc_write_blocks,
},
.block_size = EMMC_BLOCK_SIZE,
.block_size = MMC_BLOCK_SIZE,
};
static const io_uuid_spec_t bl31_uuid_spec = {

4
plat/hisilicon/hikey/platform.mk
View File

@ -65,7 +65,7 @@ BL1_SOURCES += bl1/tbbr/tbbr_img_desc.c \
drivers/io/io_block.c \
drivers/io/io_fip.c \
drivers/io/io_storage.c \
drivers/emmc/emmc.c \
drivers/mmc/mmc.c \
drivers/synopsys/emmc/dw_mmc.c \
lib/cpus/aarch64/cortex_a53.S \
plat/hisilicon/hikey/aarch64/hikey_helpers.S \
@ -81,7 +81,7 @@ BL2_SOURCES += common/desc_image_load.c \
drivers/io/io_block.c \
drivers/io/io_fip.c \
drivers/io/io_storage.c \
drivers/emmc/emmc.c \
drivers/mmc/mmc.c \
drivers/synopsys/emmc/dw_mmc.c \
lib/cpus/aarch64/cortex_a53.S \
plat/hisilicon/hikey/aarch64/hikey_helpers.S \

6
plat/hisilicon/poplar/bl1_plat_setup.c
View File

@ -10,9 +10,9 @@
#include <console.h>
#include <debug.h>
#include <dw_mmc.h>
#include <emmc.h>
#include <errno.h>
#include <generic_delay_timer.h>
#include <mmc.h>
#include <mmio.h>
#include <pl061_gpio.h>
#include <platform.h>
@ -92,6 +92,7 @@ void bl1_plat_arch_setup(void)
void bl1_platform_setup(void)
{
int i;
struct mmc_device_info info;
#if !POPLAR_RECOVERY
dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
#endif
@ -105,7 +106,8 @@ void bl1_platform_setup(void)
#if !POPLAR_RECOVERY
/* SoC-specific emmc register are initialized/configured by bootrom */
INFO("BL1: initializing emmc\n");
dw_mmc_init(&params);
info.mmc_dev_type = MMC_IS_EMMC;
dw_mmc_init(&params, &info);
#endif
plat_io_setup();

7
plat/hisilicon/poplar/bl2_plat_setup.c
View File

@ -11,9 +11,9 @@
#include <debug.h>
#include <desc_image_load.h>
#include <dw_mmc.h>
#include <emmc.h>
#include <errno.h>
#include <generic_delay_timer.h>
#include <mmc.h>
#include <mmio.h>
#include <optee_utils.h>
#include <partition/partition.h>
@ -333,6 +333,8 @@ void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
void bl2_early_platform_setup(meminfo_t *mem_layout)
{
struct mmc_device_info info;
#if !POPLAR_RECOVERY
dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
#endif
@ -347,7 +349,8 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
#if !POPLAR_RECOVERY
/* SoC-specific emmc register are initialized/configured by bootrom */
INFO("BL2: initializing emmc\n");
dw_mmc_init(&params);
info.mmc_dev_type = MMC_IS_EMMC;
dw_mmc_init(&params, &info);
#endif
plat_io_setup();

4
plat/hisilicon/poplar/include/hi3798cv200.h
View File

@ -67,11 +67,11 @@
#define EMMC_DESC_SIZE U(0x00100000) /* 1MB */
#define EMMC_INIT_PARAMS(base) \
{ .bus_width = EMMC_BUS_WIDTH_8, \
{ .bus_width = MMC_BUS_WIDTH_8, \
.clk_rate = 25 * 1000 * 1000, \
.desc_base = (base), \
.desc_size = EMMC_DESC_SIZE, \
.flags = EMMC_FLAG_CMD23, \
.flags = MMC_FLAG_CMD23, \
.reg_base = REG_BASE_MCI, \
}

8
plat/hisilicon/poplar/plat_storage.c
View File

@ -7,13 +7,13 @@
#include <arch_helpers.h>
#include <assert.h>
#include <debug.h>
#include <emmc.h>
#include <firmware_image_package.h>
#include <io_block.h>
#include <io_driver.h>
#include <io_fip.h>
#include <io_memmap.h>
#include <io_storage.h>
#include <mmc.h>
#include <mmio.h>
#include <partition/partition.h>
#include <semihosting.h>
@ -38,10 +38,10 @@ static const io_block_dev_spec_t emmc_dev_spec = {
.length = POPLAR_EMMC_DATA_SIZE,
},
.ops = {
.read = emmc_read_blocks,
.write = emmc_write_blocks,
.read = mmc_read_blocks,
.write = mmc_write_blocks,
},
.block_size = EMMC_BLOCK_SIZE,
.block_size = MMC_BLOCK_SIZE,
};
#else
static const io_dev_connector_t *mmap_dev_con;

4
plat/hisilicon/poplar/platform.mk
View File

@ -82,7 +82,7 @@ PLAT_BL_COMMON_SOURCES := \
BL1_SOURCES += \
lib/cpus/aarch64/cortex_a53.S \
drivers/arm/pl061/pl061_gpio.c \
drivers/emmc/emmc.c \
drivers/mmc/mmc.c \
drivers/synopsys/emmc/dw_mmc.c \
drivers/io/io_storage.c \
drivers/io/io_block.c \
@ -94,7 +94,7 @@ BL1_SOURCES += \
BL2_SOURCES += \
drivers/arm/pl061/pl061_gpio.c \
drivers/emmc/emmc.c \
drivers/mmc/mmc.c \
drivers/synopsys/emmc/dw_mmc.c \
drivers/io/io_storage.c \
drivers/io/io_block.c \