Rename Cortex Hercules AE to Cortex 78 AE
Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
This commit is contained in:
Jimmy Brisson
Madhukar Pappireddy
parent
5ecfd89070
commit
5effe0beba
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@ -4,11 +4,11 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_HERCULES_AE_H
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#define CORTEX_HERCULES_AE_H
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#ifndef CORTEX_A78_AE_H
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#define CORTEX_A78_AE_H
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#include <cortex_a78.h>
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#define CORTEX_HERCULES_AE_MIDR U(0x410FD420)
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#define CORTEX_A78_AE_MIDR U(0x410FD420)
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#endif /* CORTEX_HERCULES_AE_H */
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#endif /* CORTEX_A78_AE_H */
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@ -7,21 +7,21 @@
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_hercules_ae.h>
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#include <cortex_a78_ae.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_hercules_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
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#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-Hercules-AE
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* The CPU Ops reset function for Cortex-A78-AE
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* -------------------------------------------------
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*/
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#if ENABLE_AMU
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func cortex_hercules_ae_reset_func
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func cortex_a78_ae_reset_func
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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@ -42,14 +42,14 @@ func cortex_hercules_ae_reset_func
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isb
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ret
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endfunc cortex_hercules_ae_reset_func
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endfunc cortex_a78_ae_reset_func
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#endif
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/* -------------------------------------------------------
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* HW will do the cache maintenance while powering down
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* -------------------------------------------------------
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*/
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func cortex_hercules_ae_core_pwr_dwn
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func cortex_a78_ae_core_pwr_dwn
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/* -------------------------------------------------------
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* Enable CPU power down bit in power control register
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* -------------------------------------------------------
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@ -59,19 +59,19 @@ func cortex_hercules_ae_core_pwr_dwn
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msr CORTEX_A78_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_hercules_ae_core_pwr_dwn
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endfunc cortex_a78_ae_core_pwr_dwn
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/*
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* Errata printing function for cortex_hercules_ae. Must follow AAPCS.
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* Errata printing function for cortex_a78_ae. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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func cortex_hercules_ae_errata_report
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func cortex_a78_ae_errata_report
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ret
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endfunc cortex_hercules_ae_errata_report
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endfunc cortex_a78_ae_errata_report
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#endif
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/* -------------------------------------------------------
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* This function provides cortex_hercules_ae specific
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* This function provides cortex_a78_ae specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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@ -79,22 +79,22 @@ endfunc cortex_hercules_ae_errata_report
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* reported.
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* -------------------------------------------------------
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*/
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.section .rodata.cortex_hercules_ae_regs, "aS"
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cortex_hercules_ae_regs: /* The ascii list of register names to be reported */
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.section .rodata.cortex_a78_ae_regs, "aS"
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cortex_a78_ae_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_hercules_ae_cpu_reg_dump
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adr x6, cortex_hercules_ae_regs
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func cortex_a78_ae_cpu_reg_dump
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adr x6, cortex_a78_ae_regs
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mrs x8, CORTEX_A78_CPUECTLR_EL1
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ret
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endfunc cortex_hercules_ae_cpu_reg_dump
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endfunc cortex_a78_ae_cpu_reg_dump
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#if ENABLE_AMU
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#define HERCULES_AE_RESET_FUNC cortex_hercules_ae_reset_func
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#define A78_AE_RESET_FUNC cortex_a78_ae_reset_func
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#else
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#define HERCULES_AE_RESET_FUNC CPU_NO_RESET_FUNC
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#define A78_AE_RESET_FUNC CPU_NO_RESET_FUNC
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#endif
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declare_cpu_ops cortex_hercules_ae, CORTEX_HERCULES_AE_MIDR, \
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HERCULES_AE_RESET_FUNC, \
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cortex_hercules_ae_core_pwr_dwn
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declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \
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A78_AE_RESET_FUNC, \
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cortex_a78_ae_core_pwr_dwn
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@ -62,7 +62,7 @@ else
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lib/cpus/aarch64/neoverse_n1.S \
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lib/cpus/aarch64/neoverse_e1.S \
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lib/cpus/aarch64/neoverse_zeus.S \
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lib/cpus/aarch64/cortex_hercules_ae.S \
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lib/cpus/aarch64/cortex_a78_ae.S \
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lib/cpus/aarch64/cortex_a65.S \
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lib/cpus/aarch64/cortex_a65ae.S \
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lib/cpus/aarch64/cortex_klein.S \
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@ -121,7 +121,7 @@ else
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lib/cpus/aarch64/neoverse_n1.S \
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lib/cpus/aarch64/neoverse_e1.S \
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lib/cpus/aarch64/neoverse_zeus.S \
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lib/cpus/aarch64/cortex_hercules_ae.S \
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lib/cpus/aarch64/cortex_a78_ae.S \
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lib/cpus/aarch64/cortex_klein.S \
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lib/cpus/aarch64/cortex_matterhorn.S \
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lib/cpus/aarch64/cortex_a65.S \
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