CSS: Implement topology support for System power domain
This patch implements the necessary topology changes for supporting system power domain on CSS platforms. The definition of PLAT_MAX_PWR_LVL and PLAT_NUM_PWR_DOMAINS macros are removed from arm_def.h and are made platform specific. In addition, the `arm_power_domain_tree_desc[]` and `arm_pm_idle_states[]` are modified to support the system power domain at level 2. With this patch, even though the power management operations involving the system power domain will not return any error, the platform layer will silently ignore any operations to the power domain. The actual power management support for the system power domain will be added later. Change-Id: I791867eded5156754fe898f9cdc6bba361e5a379
This commit is contained in:
Soby Mathew
parent
f57e2db6ef
commit
5f3a60301e
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@ -44,7 +44,8 @@
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define ARM_CLUSTER_COUNT 2ull
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#define ARM_CLUSTER_COUNT 2
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#define ARM_SYSTEM_COUNT 1
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#define ARM_CACHE_WRITEBACK_SHIFT 6
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@ -54,6 +55,7 @@
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*/
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#define ARM_PWR_LVL0 MPIDR_AFFLVL0
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#define ARM_PWR_LVL1 MPIDR_AFFLVL1
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#define ARM_PWR_LVL2 MPIDR_AFFLVL2
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/*
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* Macros for local power states in ARM platforms encoded by State-ID field
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@ -179,10 +181,6 @@
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#define ADDR_SPACE_SIZE (1ull << 32)
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#define PLAT_NUM_PWR_DOMAINS (ARM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
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/*
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* This macro defines the deepest retention state possible. A higher state
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* id will represent an invalid or a power down state.
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@ -123,6 +123,11 @@ void arm_configure_mmu_el3(unsigned long total_base,
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(((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \
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arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
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/* Make composite power state parameter till power level 2 */
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#define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
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(((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \
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arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
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#endif /* __ARM_RECOM_STATE_ID_ENC__ */
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@ -38,9 +38,13 @@
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#include <v2m_def.h>
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#include "../fvp_def.h"
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/* Required platform porting definitions */
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#define PLAT_NUM_PWR_DOMAINS (ARM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
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/*
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* Most platform porting definitions provided by included headers
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* Other platform porting definitions are provided by included headers
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*/
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/*
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@ -41,9 +41,13 @@
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#include <v2m_def.h>
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#include "../juno_def.h"
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/* Juno supports system power domain */
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
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#define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \
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ARM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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/*
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* Most platform porting definitions provided by included headers
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* Other platform porting definitions are provided by included headers
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*/
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/*
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@ -51,18 +51,23 @@
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* The table must be terminated by a NULL entry.
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*/
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const unsigned int arm_pm_idle_states[] = {
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/* State-id - 0x01 */
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arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET,
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ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
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/* State-id - 0x02 */
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arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
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ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
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/* State-id - 0x22 */
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arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
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ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
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/* State-id - 0x001 */
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arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
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ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
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/* State-id - 0x002 */
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arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
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ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
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/* State-id - 0x022 */
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arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
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ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
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#if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1
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/* State-id - 0x222 */
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arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
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ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
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#endif
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0,
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};
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#endif
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#endif /* __ARM_RECOM_STATE_ID_ENC__ */
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/*******************************************************************************
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* Handler called when a power domain is about to be turned on. The
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@ -31,26 +31,28 @@
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#include <plat_arm.h>
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/*
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* On ARM platforms, by default the cluster power level is treated as the
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* On ARM CSS platforms, by default, the system power level is treated as the
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* highest. The first entry in the power domain descriptor specifies the
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* number of cluster power domains i.e. 2.
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* number of system power domains i.e. 1.
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*/
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#define CSS_PWR_DOMAINS_AT_MAX_PWR_LVL ARM_CLUSTER_COUNT
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#define CSS_PWR_DOMAINS_AT_MAX_PWR_LVL ARM_SYSTEM_COUNT
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/*
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* The CSS power domain tree descriptor. The cluster power domains are
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* arranged so that when the PSCI generic code creates the power domain tree,
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* the indices of the CPU power domain nodes it allocates match the linear
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* indices returned by plat_core_pos_by_mpidr() i.e.
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* CLUSTER1 CPUs are allocated indices from 0 to 3 and the higher indices for
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* CLUSTER0 CPUs.
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* The CSS power domain tree descriptor for dual cluster CSS platforms.
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* The cluster power domains are arranged so that when the PSCI generic
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* code creates the power domain tree, the indices of the CPU power
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* domain nodes it allocates match the linear indices returned by
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* plat_core_pos_by_mpidr() i.e. CLUSTER1 CPUs are allocated indices
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* from 0 to 3 and the higher indices for CLUSTER0 CPUs.
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*/
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const unsigned char arm_power_domain_tree_desc[] = {
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/* No of root nodes */
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CSS_PWR_DOMAINS_AT_MAX_PWR_LVL,
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/* No of children for the first node */
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/* No of children for the root node */
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ARM_CLUSTER_COUNT,
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/* No of children for the first cluster node */
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PLAT_ARM_CLUSTER1_CORE_COUNT,
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/* No of children for the second node */
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/* No of children for the second cluster node */
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PLAT_ARM_CLUSTER0_CORE_COUNT
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};
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