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Merge "Prevent speculative execution past ERET" into integration

This commit is contained in:
Soby Mathew 2020-01-24 10:04:10 +00:00 committed by TrustedFirmware Code Review
parent 4e1b0b193c f461fe346b
commit 5f3ed6aaed
11 changed files with 28 additions and 19 deletions
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4
bl1/aarch64/bl1_exceptions.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -202,7 +202,7 @@ debug_loop:
ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
eret
exception_return
endfunc smc_handler64
unexpected_sync_exception:

4
bl2/aarch64/bl2_el3_entrypoint.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -95,5 +95,5 @@ func bl2_run_next_image
ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
eret
exception_return
endfunc bl2_run_next_image

2
bl31/aarch64/runtime_exceptions.S
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@ -456,7 +456,7 @@ smc_unknown:
smc_prohibited:
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
mov x0, #SMC_UNK
eret
exception_return
#if DEBUG
rt_svc_fw_critical_error:

4
bl32/tsp/aarch64/tsp_exceptions.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -64,7 +64,7 @@
smc #0
interrupt_exit_\label:
restore_caller_regs_and_lr
eret
exception_return
.endm
.globl tsp_exceptions

11
include/arch/aarch64/asm_macros.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -218,4 +218,13 @@
ret
.endm
/*
* Macro for mitigating against speculative execution beyond ERET.
*/
.macro exception_return
eret
dsb nsh
isb
.endm
#endif /* ASM_MACROS_S */

4
lib/cpus/aarch64/cortex_a76.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -85,7 +85,7 @@
bic x3, x2, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
csel x3, x3, x1, eq
msr CORTEX_A76_CPUACTLR2_EL1, x3
eret /* ERET implies ISB */
exception_return /* exception_return contains ISB */
.endif
1:
/*

4
lib/cpus/aarch64/neoverse_n1.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -553,7 +553,7 @@ func neoverse_n1_errata_ic_trap_handler
*/
esb
#endif
eret
exception_return
1:
ret
endfunc neoverse_n1_errata_ic_trap_handler

4
lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -48,7 +48,7 @@ vector_base wa_cve_2017_5715_mmu_vbar
ccmp w0, w1, #0, eq
/* Static predictor will predict a fall through */
bne 1f
eret
exception_return
1:
.endif

2
lib/el3_runtime/aarch64/context.S
View File

@ -534,6 +534,6 @@ func el3_exit
*/
esb
#endif
eret
exception_return
endfunc el3_exit

4
plat/renesas/rcar/aarch64/plat_helpers.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -189,7 +189,7 @@ func bl2_enter_bl31
ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
msr elr_el3, x0
msr spsr_el3, x1
eret
exception_return
endfunc bl2_enter_bl31
/* -----------------------------------------------------

4
services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -87,7 +87,7 @@ vector_entry SynchronousExceptionA64, .spm_shim_exceptions
do_smc:
mrs x30, tpidr_el1
smc #0
eret
exception_return
/* AArch64 system instructions trap are handled as a panic for now */
handle_sys_trap: