rockchip/rk3399: Save space for DRAM suspend data
This removes the space allocation for the unused PHY register space. For instance in PHY registers 0-127, only 0-90 are used, so don't save the 91-127 registers. This saves about 1.6KB of space. Change-Id: I0c9f6d9bed8f0c1f3b8b805dfb10cf0c06208919 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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@ -24,7 +24,17 @@ struct rk3399_ddr_pctl_regs {
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};
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struct rk3399_ddr_publ_regs {
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uint32_t denali_phy[PHY_REG_NUM];
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/*
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* PHY registers from 0 to 511.
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* Only registers 0-90 of each 128 register range are used.
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*/
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uint32_t phy0[4][91];
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/*
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* PHY registers from 512 to 895.
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* Only registers 0-37 of each 128 register range are used.
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*/
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uint32_t phy512[3][38];
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uint32_t phy896[63];
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};
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struct rk3399_ddr_pi_regs {
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@ -495,9 +495,9 @@ static __sramfunc void pctl_cfg(uint32_t ch,
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struct rk3399_sdram_params *sdram_params)
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{
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const uint32_t *params_ctl = sdram_params->pctl_regs.denali_ctl;
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const uint32_t *params_phy = sdram_params->phy_regs.denali_phy;
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const uint32_t *params_pi = sdram_params->pi_regs.denali_pi;
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uint32_t tmp, tmp1, tmp2;
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const struct rk3399_ddr_publ_regs *phy_regs = &sdram_params->phy_regs;
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uint32_t tmp, tmp1, tmp2, i;
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/*
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* Workaround controller bug:
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@ -509,9 +509,8 @@ static __sramfunc void pctl_cfg(uint32_t ch,
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sram_regcpy(PI_REG(ch, 0), (uintptr_t)¶ms_pi[0],
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PI_REG_NUM);
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mmio_write_32(PHY_REG(ch, 910), params_phy[910]);
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mmio_write_32(PHY_REG(ch, 911), params_phy[911]);
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mmio_write_32(PHY_REG(ch, 912), params_phy[912]);
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sram_regcpy(PHY_REG(ch, 910), (uintptr_t)&phy_regs->phy896[910 - 896],
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3);
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mmio_clrsetbits_32(CTL_REG(ch, 68), PWRUP_SREFRESH_EXIT,
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PWRUP_SREFRESH_EXIT);
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@ -538,14 +537,15 @@ static __sramfunc void pctl_cfg(uint32_t ch,
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break;
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}
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sram_regcpy(PHY_REG(ch, 896), (uintptr_t)¶ms_phy[896], 63);
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sram_regcpy(PHY_REG(ch, 0), (uintptr_t)¶ms_phy[0], 91);
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sram_regcpy(PHY_REG(ch, 128), (uintptr_t)¶ms_phy[128], 91);
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sram_regcpy(PHY_REG(ch, 256), (uintptr_t)¶ms_phy[256], 91);
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sram_regcpy(PHY_REG(ch, 384), (uintptr_t)¶ms_phy[384], 91);
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sram_regcpy(PHY_REG(ch, 512), (uintptr_t)¶ms_phy[512], 38);
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sram_regcpy(PHY_REG(ch, 640), (uintptr_t)¶ms_phy[640], 38);
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sram_regcpy(PHY_REG(ch, 768), (uintptr_t)¶ms_phy[768], 38);
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sram_regcpy(PHY_REG(ch, 896), (uintptr_t)&phy_regs->phy896[0], 63);
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for (i = 0; i < 4; i++)
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sram_regcpy(PHY_REG(ch, 128 * i),
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(uintptr_t)&phy_regs->phy0[i][0], 91);
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for (i = 0; i < 3; i++)
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sram_regcpy(PHY_REG(ch, 512 + 128 * i),
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(uintptr_t)&phy_regs->phy512[i][0], 38);
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}
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static __sramfunc int dram_switch_to_next_index(
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@ -652,15 +652,15 @@ static __sramfunc int pctl_start(uint32_t channel_mask,
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void dmc_save(void)
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{
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struct rk3399_sdram_params *sdram_params = &sdram_config;
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struct rk3399_ddr_publ_regs *phy_regs;
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uint32_t *params_ctl;
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uint32_t *params_pi;
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uint32_t *params_phy;
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uint32_t refdiv, postdiv2, postdiv1, fbdiv;
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uint32_t tmp, ch, byte;
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uint32_t tmp, ch, byte, i;
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phy_regs = &sdram_params->phy_regs;
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params_ctl = sdram_params->pctl_regs.denali_ctl;
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params_pi = sdram_params->pi_regs.denali_pi;
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params_phy = sdram_params->phy_regs.denali_phy;
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fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff;
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tmp = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1));
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@ -687,14 +687,15 @@ void dmc_save(void)
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/* mask DENALI_PI_00_DATA.START, only copy here, will trigger later*/
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params_pi[0] &= ~(0x1 << 0);
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sram_regcpy((uintptr_t)¶ms_phy[0], PHY_REG(0, 0), 91);
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sram_regcpy((uintptr_t)¶ms_phy[128], PHY_REG(0, 128), 91);
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sram_regcpy((uintptr_t)¶ms_phy[256], PHY_REG(0, 256), 91);
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sram_regcpy((uintptr_t)¶ms_phy[384], PHY_REG(0, 384), 91);
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sram_regcpy((uintptr_t)¶ms_phy[512], PHY_REG(0, 512), 38);
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sram_regcpy((uintptr_t)¶ms_phy[640], PHY_REG(0, 640), 38);
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sram_regcpy((uintptr_t)¶ms_phy[768], PHY_REG(0, 768), 38);
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sram_regcpy((uintptr_t)¶ms_phy[896], PHY_REG(0, 896), 63);
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for (i = 0; i < 4; i++)
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sram_regcpy((uintptr_t)&phy_regs->phy0[i][0],
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PHY_REG(0, 128 * i), 91);
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for (i = 0; i < 3; i++)
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sram_regcpy((uintptr_t)&phy_regs->phy512[i][0],
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PHY_REG(0, 512 + 128 * i), 38);
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sram_regcpy((uintptr_t)&phy_regs->phy896[0], PHY_REG(0, 896), 63);
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for (ch = 0; ch < sdram_params->num_channels; ch++) {
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for (byte = 0; byte < 4; byte++)
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@ -703,10 +704,10 @@ void dmc_save(void)
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}
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/* set DENALI_PHY_957_DATA.PHY_DLL_RST_EN = 0x1 */
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params_phy[957] &= ~(0x3 << 24);
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params_phy[957] |= 1 << 24;
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params_phy[896] |= 1;
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params_phy[896] &= ~(0x3 << 8);
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phy_regs->phy896[957 - 896] &= ~(0x3 << 24);
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phy_regs->phy896[957 - 896] |= 1 << 24;
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phy_regs->phy896[0] |= 1;
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phy_regs->phy896[0] &= ~(0x3 << 8);
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}
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__sramfunc void dmc_restore(void)
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